04-01-2013, 02:15 PM
8-by-8 Bit Booth Multiplier
8-by-8 Bit Booth.doc (Size: 1.06 MB / Downloads: 377)
Abstract
This project describes the design of an 8 bit Multiplier A*B circuit using Booth Multiplication. The multiplier receives operands A and B, and outputs result Z. After registering operand A and B, load A to Booth Algorithm Block. Then use Booth algorithm to transform A and multiply by B. The output Z is the result of the original A*B.
Booth algorithm and architecture of the design are presented in details. In order to realize the multiplier, VHDL is introduced. The tests of the circuit show that the design can completely accord with different cases.
Timing and expand the circuit to high order like 16 by 16 bit multiplier will be also discussed in this paper.
INTRODUCTION
The objection of this project is to design an 8 bit Multiplier A*B circuit using Booth Multiplication. The Multiplier can receive 8 bit signed number operands A & B, in a register RA and RB, and output the result in 16 bit register Z. In the beginning of each multiplication cycle, the operands (A & B) are loaded parallel in the RA and RB registers. Each multiplication starts with a LOAD signal and ends with an END signal.
BOOTH ALGORITHM
As to the process of multiplying numbers, there are many algorithms to implement. In multiplying signed numbers together, special care is needed. Booth algorithm is an efficient means of multiplying signed numbers expressed in 2's complement notation. It is a powerful algorithm for signed-number multiplication, which treats both positive and negative numbers uniformly.
Booth algorithm is a method that is able to reduce the number of multiplicand multiples. This advantage can save both area and time in the circuit. For this project, the Radix-4 is used.
Table 1 is used to convert a binary number to Radix-4 number. Initially, a “0” is placed to the right most bit of the multiplier. Then 3 bits of the multiplicand is recoded according to the following equation. Equivalently, Table 1 maps the equation in details.
The Structure of Booth Multiplier
The block diagram of Booth Multiplier is shown in Figure 4.5, where RA is the register of input A, RB is the register of input B, RZ is the output register, shifter is barrel shifter (shift left by 2 bits). Depending on the booth Radix-4 encoding rule, RA should be selected and shifted by 2, -2, 0. Also, depending on those values (2, 1, 0, -1, -2), control unit can choose the MUX output.
CONCLUSION
An 8-bit by 8-bit multiplier with booth algorithm is designed, analyzed. And it has been verified by four general cases. The timing of the circuit and its expansion for more bits are discussed as well.
Using the booth algorithm to realize the 8-bit by 8-bit multiplier, it is obvious that it can save time against ordinary 8-bit by 8-bit multiplier. Meanwhile, the number of the components such as the full adder is also reduced in booth algorithm block. That means the area and power is saved.
It is easy to expand this multiplier into high order such as 16-bit by 16-bit multiplier. From the same main principle and structure, the 32-bit by 32-bit multiplier can be designed.