19-10-2016, 03:58 PM
1459920979-22.pdf (Size: 344.47 KB / Downloads: 16)
Abstract—This paper proposes a dual three-leg voltage source
inverter (VSI) based distribution static compensator (DSTATCOM)
to compensate unbalanced and nonlinear loads in threephase
four-wire distribution systems. The proposed topology uses
two three-leg inverters having common dc-link with single dc
capacitor and an additional small capacitor connected from the
negative terminal of VSI to the system neutral. The proposed
scheme with associated control algorithm has the capability to
compensate unbalanced nonlinear load and hence makes source
current as balanced sinusoidal and at desired power factor. The
control algorithm also ensures the proper sharing of reactive,
harmonics and unbalance powers between two VSIs and controls
the grid current total harmonic distortion (THD) level. The
performance of the proposed scheme has been verified using
simulation and experimental studies and results are presented.
INTRODUCTION
Distribution static compensators (DSTATCOMs) are extensively
being used for reactive, harmonic and unbalanced load
compensation in three-phase four-wire distribution systems
[1]–[5]. However, use of DSTATCOMs for high power applications
is usually limited by the available maximum current
rating of semiconductor devices and their switching characteristics.
Therefore, in order to match with high power requirements
and to avoid large capacity centralized compensators,
parallel operation of low power compensators is used [6]–
[8]. The parallel implementation of low power compensators
has many other advantages such as high redundancy, more
reliability, better ride-through capability, simpler replacement
procedures etc.
Many parallel inverter schemes for active power compensation
are reported in literature [9]–[11]. Authors in [9] describe
a reduced switch hybrid dual inverter topology with a common
dc-link for active filter operation. A shunt active compensator
scheme containing dual active filters operating in feedforward
and feedback modes has been proposed in [10]. The
advantages of using parallel voltage source inverters (VSIs)
with common dc capacitor in reducing the filter size has been
described in their work. Literature [11] reports control scheme
to reduce converter losses by separating harmonic and reactive
compensation in two VSIs with common dc-link. All these parallel active filter topologies efficiently compensate reactive
and harmonic currents. However, these schemes consider only
three-phase three-wire distribution systems and hence not
suitable for neutral current compensation. On the one hand,
the proliferation of unbalanced load in three-phase four-wire
distribution systems creates an excessive neutral current and
hence overloading the neutral conductor. The various VSI
topologies to mitigate neutral current along with power quality
compensation are four-leg VSI, three single-phase VSIs,
three-leg VSI with split capacitors, three-leg VSI with zigzag
transformer, three-leg VSI with T-connected transformer
and three-leg VSI with neutral terminal at the positive or
negative of dc bus [12]–[15]. Out of these different schemes,
three-phase four-wire split capacitor active filter topology has
gained popularity because of its less number of semiconductor
switches and independent control of inverter legs.
Parallel inverter scheme using common dc-link with split
capacitor topology has been used in unified power quality
conditioner (UPQC) applications [16]. One drawback of this
topology is the voltage unbalance between two dc storage
capacitors [17], [18]. This is due to the flow of neutral current
through one of the capacitor causing one capacitor voltage to
increase and the other to decrease. It results in unequal voltage
stress across semiconductor switches and hence degrade the
compensation performance. Suitable control schemes have
been devised to alleviate this voltage unbalance issues [17],
[18]. However it requires additional switches and control
methods . In [19], authors have used a single dc capacitor
three-leg topology to compensate unbalanced and nonlinear
load currents. This scheme uses additional three ac capacitors
in series to the inductor filter of VSI. When this scheme is to
be implemented for parallel compensators with more VSIs, the
number of series ac capacitors required will be proportionally
increased and hence increases the overall cost.
In this paper, a new topology of parallel DSTATCOM is
proposed for a three-phase four-wire distribution system. The
proposed scheme consists of two three-leg inverters having a
common dc-link with single dc capacitor. The negative terminal
of the dc-link is connected to the neutral through a small
capacitor. The rating of this additional capacitor depends on
the neutral current to be compensated. As compared with split
capacitor topology, the dc capacitor voltage unbalance issues
are avoided in this proposed scheme and at the same time, the
advantages of four-leg and split capacitor topologies are simultaneously achieved. The reference currents of two inverters are
generated using instantaneous symmetrical component theory
(ISCT) [20]. Hysteresis band current control (HBCC) [15] is
used to control VSI switches to track these reference currents.
The compensation performance of the proposed scheme is
tested through simulation and experimental studies.
II. PROPOSED TOPOLOGY
The topology of the proposed dual VSI based compensator
is shown in Fig. 1. It consists of two three-leg VSIs (Inv1 and
Inv2) with common dc-link. The Inv1 currents in three phases
are represented as if1a, if1b and if1c. The three-phase currents
of Inv2 are denoted by if2a, if2b and if2c. Here, vsa, vsb
and vsc are source voltages in a, b and c phases respectively.
The three-phase source currents are represented by isa, isb
and isc. The load consists of both unbalanced reactive and
nonlinear loads and are drawing currents ila, ilb and ilc. The
topology uses a single dc capacitor Cdc and an additional small
ac capacitor Cn, which is connected between lower leg of VSI
and neutral. The voltage across Cdc is maintained at 2×1.6×
Vm, where Vm is the peak of source phase voltage. This dc-link
voltage is denoted as 2 Vdc in further analysis of this paper. The
selection of Cdc is based on the rating of dual compensator.
The neutral capacitor Cn is chosen based on the zero sequence
current which is to be compensated. In this paper, Cdc and Cn
are selected based on the design method explained in [15].
III. MODELING AND ANALYSIS OF PROPOSED TOPOLOGY
In this analysis, one of the VSI in the proposed scheme
is considered to derive the equivalent model. The dc-link
capacitor and neutral capacitor for a single VSI is represented
as α Cdc and α Cn respectively. Where α represents the
fraction of load compensation performed by Inv1. This value
can be set based on the kVA ratings of VSIs used in dual
compensator. Let S1 and S2 be the rated kVA capacity of two