09-02-2013, 12:04 PM
A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications
A Low-Power 64-point .pdf (Size: 835.19 KB / Downloads: 45)
Abstract
4G and other wireless systems are currently hot
topics of research and development in the communication
field. Broadband wireless systems based on orthogonal
frequency division multiplexing (OFDM) often require an
inverse fast Fourier transform (IFFT) to produce multiple subcarriers.
In this paper, we present the efficient implementation
of a pipeline FFT/IFFT processor for OFDM applications.
Our design adopts a single-path delay feedback style as the
proposed hardware architecture. To eliminate the read-only
memories (ROM’s) used to store the twiddle factors, the
proposed architecture applies a reconfigurable complex
multiplier and bit-parallel multipliers to achieve a ROM-less
FFT/IFFT processor, thus consuming lower power than the
existing works. The design spends about 33.6K gates, and its
power consumption is about 9.8mW at 20MHz1.
INTRODUCTION
Discrete Fourier transform (DFT) is a very important
technique in modern digital signal processing (DSP) and
telecommunications, especially for applications in orthogonal
frequency demodulation multiplexing (OFDM) systems, such
as IEEE 802.11a/g [1], Worldwide Interoperability for
Microwave Access (WiMAX) [2], Long Term Eevolution
(LTE) [3], and Digital Video Broadcasting—Terrestrial
(DVB-T) [4]. However, DFT is computational intensive and
has a time complexity of O(N2). The fast Fourier transform
(FFT) was proposed by Cooley and Tukey [5] to efficiently
reduce the time complexity to O(Nlog 2N), where N denotes
the FFT size.
PROPOSED ARCHITECTURE
Traditional hardware implementation of FFT/IFFT
processors usually employs a ROM to look up the wanted
twiddle factors, and then wordlength complex multipliers to
perform FFT computing. However, this introduces more
hardware cost, thus a bit-parallel complex constant
multiplication scheme [8]-[11], [14]-[18] is used to improve
the foregoing issue.
Proposed Architecture
In order to improve the previous works on power reduction,
we propose a radix-2 64-point pipeline FFT/IFFT processor
with low power consumption, as shown in Fig. 2. The
proposed architecture is composed of three different types of
processing elements (PEs), a complex constant multiplier,
delay-line (DL) buffers (as shown by a rectangle with a
number inside), and some extra processing units for
computing IFFT. Here, the conjugate for extra processing
units is easy to implement, which only takes the 2’s
complement of the imaginary part of a complex value. The
divided-by-64 module can be substituted with a barrel shifter.
In addition, for a complex constant multiplier in Fig. 2, we
propose a novel reconfigurable complex constant multiplier to
eliminate the twiddle-factor ROM. This new multiplication
structure thus becomes the key component in reducing the
chip area and power consumption of our proposed FFT/IFFT
processor. The detailed functions of these modules appeared
in Fig. 2 are described in the following subsections.
CONCLUSION
A novel ROM-less and low-power pipeline 64-point
FFT/IFFT processor for OFDM applications has been
described in this paper. Considering the symmetric property of
twiddle factors in FFT, we have designed a reconfigurable
complex constant multiplier such that the size of twiddlefactor
ROM is significantly shrunk, especially no ROM is
needed in our work. This result shows that our design owns
lower hardware cost and power consumption compared to the
existing ones.