04-01-2013, 04:54 PM
A Rotation-Based BIST with Self-Feedback Logic to Achieve Complete Fault Coverage
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Abstract
This paper presents a deterministic BIST technique that
can efficiently achieve complete fault coverage without using
any storage devices. A novel test structure containing a
self-feedback logic unit and a circular shift register is
proposed by which all the required deterministic patterns can
be generated on-chip in real time. Experiments on ISCAS 85
benchmark circuits show that compared with previous work
addressing the same problem our technique requires much less
test time to achieve 100% fault coverage for all testable
stuck-at faults.
Introduction
Logic Built-In Self-Test (BIST) has been shown to be an
effective design for testability (DFT) technique in which some
on-chip test structure is used to test the digital circuit itself [1].
Pseudo-random testing based on linear feedback shift registers
(LFSRs) is commonly used as the basis of BIST due to its
simplicity and effectiveness. However a complex circuit often
contains some hard-to-detect faults that are random-pattern
resistant and thus a pseudo random test scheme usually
requires long time to reach satisfactory fault coverage.
To address this problem, in literature several techniques
have been proposed. The weighted random test method [1] is
presented to enhance the detectability of hard-to-detect faults.
This technique may require long test time for a circuit
containing many hard-to-detect faults. The mixed-mode BIST
technique [1] takes advantages of both pseudo random and
deterministic patterns to achieve complete fault coverage in a
short time. To carry out the test process, complicated control
may be required to switch between different test modes,
loading required seeds and/or reconfiguring some specific
mapping logic.
The Proposed BIST Architecture
As shown in Figure 1 the proposed BIST architecture
consists of a self-feedback logic unit (SFL), a circular shift
register (CSR), a response monitor and an on-chip BIST
control unit. The SFL along with the CSR are used to generate
all the required test patterns, and the response monitor is
employed to capture the test responses. The whole test
procedure is managed by the control unit.
In our BIST architecture all the primary inputs and scan
cells of a CUT are serially connected to form the CSR. During
test application an initial pattern stored in the CSR is circularly
shifted (rotated) by one bit per test cycle. Thus up to n-1
additional test patterns can be generated if the length of the
CSR is n. However it should be pointed out that in our
architecture full rotation is not always required for each initial
pattern. In other words, each initial pattern can have its own
rotation number in order to reach 100% fault coverage in a
shorter time. Due to this novel feature, much fewer test cycles
are required than previous work [2-5] that uses a fixed number
of shift or rotation cycles for each initial pattern or seed.
The required initial patterns for the CSR can be generated
by simply resetting the CSR or through the SFL based on the
current responses of some pre-determined internal nets. In the
latter case, some logic operations of the response bits are
employed to change the state of the CSR directly. In this work
unary logic operations including no-operation, inversion,
short-to-VDD and short-to-GND, and binary ones including
and/or, nand/nor and xor/xnor are considered. Throughout this
paper we shall define each such a logic operation of response
bit(s) as one feedback candidate. Some related definitions are
also given: a set of feedback candidates that together can
provide the required logic values of an initial pattern is defined
as a configuration; a pattern generated by the SFL via a
configuration is defined as a feedback pattern, the set
containing all feedback patterns is called the feedback test set,
and a pattern generated by a rotation operation based on a
feedback pattern is defined as a rotation pattern
Experimental Results
Experiments on ISCAS 85 circuits targeting 100% fault
coverage are conducted. We will compare the results with
some related work that also employs only deterministic
patterns but needs some space to store the required seed
patterns or initial patterns.
Table 1 shows the number of cycles to achieve 100% fault
coverage for each circuit using the proposed method.
Comparisons of our work with those in [2] and [5] are also
given. The first six columns show the circuit name CKT, the
number of input ports #IN, the number of testable faults |F|,
the pre-defined fault coverage PDFC used to determine when
to stop Phase 1, the total number of generated feedback
patterns |S|, and the total number of configurations #CF. Note
that different results may be obtained by setting different
values of PDFC. Here we use 92, 94, 96 and 98% and report
the best results. As shown in Table 1 our method can
completely test all circuits using only l or 2 configurations
except for c1908. Also the number of required feedback
patterns (|S|) is small.
Conclusions
In this paper we have developed an efficient test-per-clock
BIST technique to achieve complete fault coverage. No storage
devices are required by this technique. We employ a
self-feedback logic unit to generate a set of seed patterns based
on responses of some pre-selected internal nets. The seed
patterns are then used to generate all required test patterns
through a circular shift register. An efficient method to
concurrently determine the test patterns to be generated and
the feedback connections is provided which results in much
shorter test time or much smaller area overhead compared to
previous work.