31-05-2013, 04:05 PM
A Seminar report on 3-DIMENSIONAL INTEGRATED CIRCUITS
DIMENSIONAL INTEGRATED.doc (Size: 390 KB / Downloads: 26)
ABSTRACT
The unprecedented growth of the computer and the Information technology industry is demanding Very Large Scale Integrated (VLSI) circuits with increasing functionality and performance at minimum cost and power dissipation. VLSI circuits are being aggressively scaled to meet this Demand, which in turn has some serious problems for the semiconductor industry.
Additionally heterogeneous integration of different technologies in one single chip (SoC) is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable.
3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC). The multi-layer chip industry opens up a whole new world of design. With the Introduction of 3-D ICs, the world of chips may never look the same again.
INTRODUCTION
There is a saying in real estate; when land get expensive, multi-storied buildings are the alternative solution. We have a similar situation in the chip industry. For the past thirty years, chip designers have considered whether building integrated circuits multiple layers might create cheaper, more powerful chips.
Performance of deep-sub micrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to increasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies on one single chip is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable.The three dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize system on a chip (SoC) design. By simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved.In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.
MOTIVATION FOR 3-D ICs
The unprecedented growth of the computer and the information technology industry is demanding Very Large Scale Integrated ( VLSI ) circuits with increasing functionality and performance at minimum cost and power dissipation. Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. A significant fraction of the total power consumption can be due to the wiring network used for clock distribution, which is usually realized using long global wires.
Furthermore, increasing drive for the integration of disparate signals (digital, analog, RF) and technologies (SOI, SiGe, GaAs, and so on) is introducing various SoC design concepts, for which existing planner (2-D) IC design may not be suitable.
INTERCONNECT LIMITED VLSI PERFORMANCE
In single Si layer (2-D) ICs, chip size is continuously increasing despite reductions in feature size made possible by advances in IC technology such as lithography and etching. This is due to the ever growing demand for functionality and high performance, which causes increased complexity of chip design, requiring more and more transistors to be closely packed and connected. Small feature sizes have dramatically improved device performance. The impact of this miniaturization on the performance of interconnect wire, however, has been less positive. Smaller wire cross sections, smaller wire pitch, and longer line to traverse larger chips have increase the resistance and capacitance of these lines, resulting in a significant increase in signal propagation (RC) delay. As interconnect scaling continues, RC delay is increasingly becoming the dominant factor determining the performance of advanced IC’s.
PHYSICAL LIMITATIONS OF Cu INTERCONNECTS
At 250 nm technology node, Cu with low-k dielectric was introduced to alleviate the adverse effect of increasing interconnect delay.However,below 130nm technology node, substantial interconnect delays would result in spite of introducing these new materials, which in turn will severely limit the chip performance. Further reduction in interconnect delay is not possible.
This problem is especially acute for global interconnects, which comprise about 10% of total wiring in current architectures. Therefore, it is apparent that material limitations will ultimately limit the performance improvement as technology scales. Also, the problem of long lossy lines cannot be fixed by simply widening the metal lines and by using thicker interlayer dielectric, since this will leas to an increase in the number of metal layers. This will result in an increase in complexity, reliability and cost.
SCOPE OF THIS STUDY
A 3D solution at first glance seems an obvious answer to the interconnect delay problem. Since chip size directly affects the inter connect delay, therefore by creating a second active layer, the total chip footprint can be reduced, thus shortening critical inter connects and reducing their delay. However, in today’s microprocessor, the chip size is not just limited by the cell size ,but also by how much meta is required to connect the cells. The transistors on the Si surface are not actually packed to maximum density, but are spaced apart to allow metal lines above to connect one transistor or one cell to another .The meal required on a chip for inter connections is determined not only by the number of gates ,but also by other factors such as architecture, average fan-out, number of I/O connections, routing complexity, etc Therefore, it is not obvious that using a 3D structure the chip size will be reduced.
PRESENT SCENARIO OF THE 3-D IC INDUSTRY
Many companies are working on the 3-D chips ,including groups at Massachusetts institute of technology (MIT),international business machines(IBM). Rensselar Polytechnic and SUNY Albany are also doing research on techniques for bonding conventional chips together to form multiple layers .whichever approach ultimately wins ,the multilayer chip building technology opens up a whole new world of design .However ,the Santa Clara, California US based startup company matrix semiconductor will bring the first multilayer chip to the market ,while matrix’s techniques will not likely result in more computing power ,they will produce cheaper chips for certain applications, like memory used in digital cameras , personal digital assistants ,cellular phones ,hand held gaming devices ,etc .matrix has adapted the technology developed for making flat –panel liquid crystal displays to build chips with multilayer of circuitry.
The company’s first products will be memory chips called 3-Dmemory, for consumer electronics like digital cameras and audio players. current flash memory cards for such devices are rewritable but expensive .however the newly produced chips will cost ten times less, about as much as an audio tape or a roll of film, but will only record information once. The cost is so largely because the stacked chips contain the same amount of circuitry as flash cards but use a much smaller area of the extremely expensive silicon wafers that form the basis for all silicon chips. The chips will also offer a permanent record of the images and sounds users record. The amount of computing power the company can ultimately build in to its chips could be limited .the company hopes to eventually build chips for cell phones, or low performance micro processors like those found in appliances; such chips would be about one tenth as expensive as current ones.