14-05-2012, 04:14 PM
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
vlsi_design_lp.ppt (Size: 624.5 KB / Downloads: 30)
Motivation
Existing linear programming techniques eliminate glitches, but may insert delay buffers when overall circuit delay is constrained.
Delay buffers consume power themselves and thus reduce power saving – also chip area increases.
Power consumption due to glitches can exceed 30-40% of total power consumption.
Example: c1355, a 619-gate circuit needed 224 buffers -- 36 % increase in gates – for 42% power saving and no IO delay increase.
Problem Statement
Find a linear program (LP) to determine gate delays in a CMOS circuit such that:
All glitches are eliminated
No delay buffers are inserted in the circuit
Circuit operates at the highest possible speed permitted by the device technology.
Gate Input Differential Delay Upper Bound
It is a measure of the maximum difference in delay of any two IO paths through the gate, that can be designed in a given CMOS technology.
Arbitrary input delays cannot be realized in practice due to the technology limitation at the transistor and layout levels.
The bound ub is the limit of flexibility allowed by the technology to the designer at the transistor and layout levels.
The following feasibility condition must be imposed while determining delays for glitch suppression: