18-05-2012, 12:59 PM
Cache Organization for Chip Multiprocessors
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INTRODUCTION
chip Multiprocessors (CMPs) are rapidly becoming
mainstream thanks to their ability to leverage the
parallelism of multithreading and multitasking to achieve
higher performance within a given power envelope. This
paradigm shift towards on-chip mutli-processing
environments introduces new computer architecture
challenges. In particular, cache data access is often a principal
bottleneck in such systems, as multiple threads compete for
limited on-die memory resources and accessibility. Hence,
CMP-tailored cache architecture, organization, and
management are critical for system performance with the
CMP paradigm. This paper introduces a new memory
subsystem architecture for the emerging CMP environment.
MEMORY ACCESS CHARACTERIZATION
In this section, we characterize memory access patterns
occurring in multithreaded workloads. We study sample
scientific benchmarks from the Splash-2 and SPEComp kits,
as well as three commercial workloads
SUMMARY AND FUTURE DIRECTIONS
The shift towards Chip Multi Processors makes the on-chip
memory system a primary performance bottleneck. This shift
calls for a new approach to cache design, in which cache
architecture will be tailored and optimized for the
multiprocessing environment. We have proposed partitioning
the cache in CMPs according to the level of data sharing. This
approach is motivated by the observation that, in many
multithreaded applications, a small set of shared cache lines
accounts for a significant portion of the memory accesses. We
have presented Nahalal – a novel CMP cache architecture and
floorplan that exhibits shorter access distances to shared data
compared to the conventional CMP with cache-in-the-middle
(CIM) architecture.