12-09-2013, 03:32 PM
Combinational Logic Implementation Technologies
Logic Implementation.ppt (Size: 640.5 KB / Downloads: 140)
Programmable Arrays of Logic Gates
Until now, we learned about designing Boolean functions using discrete logic gates
We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure
Specific functions can be programmed
Can use programmable logic arrays (PLA) or programmable array logic (PAL)
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes
Summary
Review of Combinational Logic Technologies
Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
Multiplexers/Decoders
ROM
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, 5.5 5.6, 5.7, 6.2