06-02-2016, 03:32 PM
Aim
To design time constrained FSK system and generate and transmit many number of FSK signals using verilog HDL and implementing it on FPGA.
Contents
1.Introduction
2.Block Diagram
3.RF Transmitter & Receiver
4.DC Motor driver & Motor
5.Communication
6.FPGA &Software
7.Advantages & Disadvantages
8.Applications
Introduction
Wireless Communication
Digital Communication.
FSK