14-08-2012, 12:53 PM
DESIGN AND IMPLEMENTATION OF LOW POWER AND AREA EFFICIENT ADDER AND VEDIC MULTIPLIER FOR FFT
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ABSTRACT
The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes. Resulted in the integration of a number of processor cores into one chip. This load is reduced by supplementing the main processor with Co-Processor. The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in application and the speed of FFT depends greatly on the multiplier and adder. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. It is used for design a multiplier. Carry select adder (CSLA) is the fastest adder used to perform an arithmetic functions. The proposed design has reduced area and power as compared with the regular Adders and Multipliers. This work evaluates the performance of the proposed designs in terms of delay, area, power.