01-05-2012, 11:55 AM
DESIGN AND SIMULATION OF 4:1MUX
THEORY:
A multiplexor or MUX is a logic component that has several inputs but only a single output. A MUX provides the capability to direct one of the inputs to the output .This is accomplished by using a control bit word that allows us to select which input will be connected to the output.
Here we will design the 4:1 MUX for this the input path is labeledas A, B, C, D and the output is denoted as Y. The value of the select word SL(1 down to 0) allows us to choose one of the paths and direct it to the output. If value of the SL is 00 then output must be A,if the value of SL is 01 then the output is B, if the value of the SL is 10 then its corresponding output is C and finally if SL is 11 then its value is D.
Similarly larger MUX will be created in the same manner the important thing in all about its selector lines.
CONCLUSION:
After getting the test bench waveform and RTL schematic of the required experiment (4:1 MUX) the program is successfully downloaded to the FPGA kit.