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Abstract:
Various class AB two-stage op-amps with high and a few symmetrical slew rate and very easy style unit of measurement introduced throughout this temporary.A current replicating branch with scaled-down transistors at the side of adaptative lots is utilized to implement a push–pull output stage with most output current again and again on the far side the bias current. Post layout simulation and live results unit of meaurement conferred and verify a 400%–500% slew rate and 80%–100% GB sweetening with exclusively baseball game any quiescent power dissipation and a couple of hundredth substance area increase
.INTRODUCTION:
1.1 DIFFERENTIAL AMPLIFIER
Differential amplifier is one of the most important circuits in analog domain. As its name suggests it only processes the difference between the two input signals. It cancels out the common voltage applied to both inputs. But, practically there always exists some amount of common voltage both at the inputs. As it cancels most of the common voltage at the input hence, noise and bias voltages are cancelled out. Most of the electronic circuits use differential amplifiers.
The output of the differential amplifier is given by,
(1.1)
Ideally,
Where Ac is the common mode gain of the amplifier and Ad is the differential mode gain of the amplifier. When using a differential amplifier it is desirable to null out noise and bias voltages that appear on both inputs so a low common-mode gain is usually considered good. The common-mode rejection ratio is usually defined as the ratio between differential-mode gain and common-mode gain and it characterizes the efficiency of the
amplifier in refusing voltages that are common to both inputs from affecting the output. Common-mode rejection ratio (CMRR) is given by
CMRR=A_V/A_D (1.2)
For an ideal differential amplifier Ac should be zero and CMRR should be infinite. A differential amplifier must have two inputs and one or two output terminals. Generally, it is used as the input stage of many analog circuits, as it has high differential gain, very high input impedance, also low output impedance and high noise cancellation.
The gain of the differential amplifier is given by,
(1.3)
Where is the transconductance of the input differential pair.
6 CAUSES OF OFFSET VOLTAGE
The cause of input offset voltage is due to the inherent mismatch of input transistors & components during silicon die fabrication and stresses retained on the die during the packaging process. These effects collectively generate a mismatch of the bias currents which flows through the input circuit & primarily the input devices; resulting in a voltage differential at input terminals of the opamp. VIO has been reduced with modern manufacturing processes through increased matching & improved package materials and assembly.
Typically, most opamps consists of a differential-pair amplifier as the input stage. where Q1 (+ or non-inverting input terminal) and Q2 (– or inverting input terminal) are MOS transistors. The input terminals of the opamp are gates of these transistors. The current source biases the transistors and each leg of the circuit is balanced so that one half of the current flows through each transistor (IQ1= IQ2= IDC/2) and the inverting & non-inverting inputs are at the same potential. Mismatches in R, Q1, and Q2 unbalance this current. The gate voltages of the transistors then become unequal, creating the small differential voltage, VIO.
The offset can be categorized into two parts, i.e random and systematic. Systematic offset causes due to channel length modulation of transistors. It arises due to the nonlinear operating characteristics of the devices or due to the influence of parasitic in the device path or signal path.On the other hand, random offset causes due to variations of physical parameters of the transistors after fabrication. This is the result of the stochastic nature of many physical processes. The stochastic nature of the charge carriers of a conductor results in various types of noise signals. During fabrication process, the stochastic nature of the physical phenomena causes random variation of the fabricated chip and mismatches between same size transistors.
2.EXISTING SYSTEM
2.1.CONVENTIONAL TWO STAGE MILLER OPAMP
Very efficient schemes have been reported to achieve high symmetrical slew rate in single-stage opamps. A drawback of single-stage op-amps based on this technique is that only relatively low open-loop gain is possible since the inclusion of output cascading transistors to increase the output resistance . Would seriously limit the maximum output current and the slew rate enhancement factor. The conventional class-A two-stage Miller-compensated op-amp figure 2. is characterized by a highly asymmetrical slew rate with large positive slew rate and much lower negative slew rate given by SR-=2 / ,where is the bias current. This low negative-slew rate is due to the fact that the output nMOS transistor (MoN) acts as a dc current source with value 2 Slew rate can only be increased in class A op-amps by increasing .
3.1TWO STAGE CLASS AB OPAMP WITH CURRENT REPLICATION BRANCH
WITH ADAPTATIVE LOAD1
As a first step to achieve class AB operation, the output transistor MoN can be transformed into an active amplifying device by simply adding a (scaled down) current replicating branch formed by M2R and MoNR. This transfers current variations Ia in M1-M2 to the output transistor MoN and increases the maximum positive output current by 2 .
The maximum negative cu\]
the only node with gain in the current replicating branch is from the gate to the drain of MoN, and at high frequencies Miller compensation causes MoP to behave as low-impedance diode-connected load. This reduces the gain between the gate of MoN (node and the opamp’s output terminal to approximately a unity value and prevents Miller multiplication by a large factor on node (which is a low impedance node) at high frequencies. The current replicating branch has negligible dimensions reducing area and static power consumption.
In order to achieve large negative-output currents (and correspondingly large negative slew rate), nonlinear adaptive loads can be used similarly to the technique introduced in and also reported. This modification is discussed next.
class AB operation can be achieved by including an adaptive load at the input stage. In both cases, the adaptive loads exploit the large variation of output resistance of transistors between triode and saturation regions. Bias voltage sets these transistors at the boundary between triode and saturation regions in quiescent conditions. With both schemes, a current increase in or causes transistors or to go in triode mode and to develop large drain-source voltages. These changes cause large variations at nodes a and b, which lead to large currents in the output transistors MoP and, thanks to the current replicating branch, MoN.