18-07-2014, 12:47 PM
Design and Implementation of Interfacing two FPGAs
Design and Implementation.docx (Size: 983.19 KB / Downloads: 12)
Abstract
As FPGA performance and capabilities have increased substantially in recent years, FPGA-based designs are employed to implement complex functions and designs. The objective of our work is to design an interface between two FPGAs using I/O interface available inside FPGAs for the purpose of reliable communication. The two FPGAs will be connected via RS-232 port, to transfer data from one FPGA to another and vice versa. Our goal is to get a simple and reliable connection when two FPGAs communicate. The data information is created using Random Number Generator. We implemented our design using two Altera FPGA boards, implemented in VerilogTM language. Dynamic simulations were performed to verify the correctness
INTRODUCTION
As communication between devices has taken a great role to accomplish a complex task, the FPGA boards become widely used in terms of available reconfigurable hardware resources to implement communication and transfer data between multi FPGA and other devices.
In this paper, we introduce an interface design between two
Altera FPGA boards via RS-232 communication, where RS-
232 serial communication has advantages of low cost and simplicity. The two FPGAs can communicate with each other and exchange information. Figure 1 shows the design of the connected FPGAs, where the transmit line of the serial RS-232
in the first FPGA is connected to the serial receive line in the second FPGA, the data terminal ready line in the first FPGA is connected to the data set ready line in the second FPGA. The transceiver chip module serves as the intermediary connection node to transform the serial data between the two FPGAs.
Connecting FPGAs enables devices to communicate with each other over a serial data bus without data loss, as well as enabling faster devices to communicate with slower ones.
RELATED WORK
Different techniques have been suggested to connect FPGAs in the literature. The goal of all these techniques is to establish a connection channel to send and receive data efficiently. In this section, we will present some related work and highlight the closest work to ours.
In [1], the authors proposed that there has been increasing interest in computing engines based on (FPGA). An FPGA- based computing system consists of multiple FPGAs which require interconnections among them. To implement circuits that cannot fit onto a single FPGA chip, the field programmable interconnect chip (FPIC) was introduced. Large circuits are divided into several parts, and each part is implemented in a separate FPGA chip. An FPIC is used to interconnect these FPGAs on a printed circuit board.
Mak and Wong in [2] showed that the hardware emulator consists of a large number of FPGAs interconnected either directly or indirectly through. Even running at a few hundred kilohertz, a hardware emulator still evaluates input vectors much faster than simulation software does (as much as 105 times faster). A logic emulator consists of a set of FPGAs and a set of FPICs. There are two major steps in logic emulation: A large design is partitioned into parts which can fit inside a single FPGA then Board-level routing is performed to connect the signals between the FPGA chips. The I/O-pins of each FPGA are evenly divided into proper subsets. The pins of a crossbar can be connected only to the same subset of pins on each FPGA.
FPGAS CONNECTION
We connect one Altera FPGA board to the PC using USB connector [JTAG connector]. JTAG (Joint Test Action Group) connector is an IEEE standard (1149.1) developed to solve electronic boards manufacturing issues. Altera FPGA devices are designed to have JTAG instructions precedence over any device configuration mode, therefore JTAG configuration can take place without waiting for other configuration modes to complete.
The JTAG cable has a USB male type A universal plug that connects to the PC USB port, and mini-male USB type B universal plug that connects to the FPGA board where data is downloaded from the USB port from the PC through the USB- Blaster cable to the FPGA board. Also, we will connect the two FPGA boards via Ethernet. The idea from this is to exchange the data between the two boards. Therefore; our connection will be made via Ethernet 10/100 PHY chips. The FPGA board
Transmitter
The Transmitter module starts when the TxD_start signal is asserted; this signal is active when data is transmitted. It takes a byte of data and sends them serially. The busy signal is asserted while a transmission occurs. At busy status the transmitter does not deposit a new character for transmission until the previous one has been completed, and we have 2 stop bits to indicate that the one byte is finished.
As we had mentioned before there are two basic modules to allow two FPGAs communicate and exchange data the Receiver module and The Transmitter module.
Receiver
The Receiver task is to look for the incoming signal for the beginning of the start bit. The Receiver module assembles data that comes in the receiver line until it receives the whole sent data then the data ready is asserted for one clock and the data sent via the data bus. After one clock, new data may come and shuffle the pervious data. Figure 4 gives illustration about these modules.
When the Transmitter module starts execution when TxD_start from switch is asserted if it is one reads input from switches then output these inputs to the TxD, until the stop bit is detected.
The Receiver module starts execution when it receives bit from RxD and if the received bit is a start bit, then it changes the state to start state. Otherwise it waits until start bit is detected. Then it continues to receive the data from RxD and save the received bits in the state and if the stop bit is detected then the end of the byte is determined. Finally it shows the result on the output LEDs as shown in Figure
ROLL DICE GAME
die generates a random integer from one to six. Each probability of those values is equal. The roll dice game is our work's application which makes is appropriate as gambling devices for games. It shows how the two FPGAs interface with each other and how to transmit and receive data between them.
The idea from our game to show how the two players roll dice and the one who will get the largest number wins the game. The inputs to the dice game come from two switches; a roll switch and a reset switch. The reset switch is used to initiate a new game and the roll switches to roll the dice toss generate the number. The output of the roll dice game display on the LCD of the FPGA showing who is the winner and who is the loser.
To generate a random number of a range from 1-6 a linear feedback shift register (LFSR) is used. LFSR is a shift register whose input bit is driven by the exclusive-or (XOR) of two bits of the overall shift register value. Because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its previous state. An LFSR with an XOR feedback function produce a sequence of bits which appears random and which has a very long cycle
CONCLUSIONS
In this paper, we described the design of RS-232 asynchronous communication. The most significant aspect of it is that the transmitter and receiver clock are independent and are not synchronized. In fact, there is no need to be a timing relationship between successive bytes of data. Individual byte may be separated by any arbitrary idle period, where both transmitter and receiver have own clock but it requires start and stop bits which provides byte timing and increases overhead. While synchronous communication is more complex interface timing information is accurately aligned to the received data,