29-04-2014, 12:25 PM
Design of Low Power TPG Using LP-LFSR
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Abstract
This paper presents a novel test pattern generator
which is more suitable for built in self test (BIST) structures used
for testing of VLSI circuits. The objective of the BIST is to
reduce power dissipation without affecting the fault coverage.
The proposed test pattern generator reduces the switching
activity among the test patterns at the most. In this approach, the
single input change patterns generated by a counter and a gray
code generator are Exclusive–ORed with the seed generated by
the low power linear feedback shift register [LP-LFSR]. The
proposed scheme is evaluated by using, a synchronous pipelined
4x4 and 8x8 Braun array multipliers. The System-On-Chip
(SOC) approach is adopted for implementation on Altera Field
Programmable Gate Arrays (FPGAs) based SOC kits with
Nios II soft-core processor. From the implementation results, it is
verified that the testing power for the proposed method is
reduced by a significant percentage.
INTRODUCTION
The main challenging areas in VLSI are performance, cost,
testing, area, reliability and power. The demand for portable
computing devices and communication system are increasing
rapidly. These applications require low power dissipation for
VLSI circuits [1]. The ability to design, fabricate and test
Application Specific Integrated Circuits (ASICs) as well as
FPGAs with gate count of the order of a few tens of millions
has led to the development of complex embedded SOC.
Hardware components in a SOC may include one or more
processors, memories and dedicated components for
accelerating critical tasks and interfaces to various peripherals.
One of the approaches for SOC design is the platform based
approach. For example, the platform FPGAs such as Xilinx
Virtex II Pro and Altera Excalibur include custom designed
fixed programmable processor cores together with millions of
gates of reconfigurable logic devices.
DESIGN OF MULTIPLIER
Multipliers are widely used in DSP operations such as
convolution for filtering, correlation and filter banks for multi
rate signal processing. Without multipliers, no computations
can be done in DSP applications. For that reason, multipliers
are chosen for testing in our proposed design.
PROPOSED METHOD
Because of simplicity of the circuit and less area
occupation, linear feedback shift register [LFSR] is used at the
maximum for generating test patterns. In this paper, we
proposed a novel architecture which generates the test patterns
with reduced switching activities. LP-TPG structure consists
of modified low power linear feedback shift register (LP-
LFSR), m-bit counter, gray counter, NOR-gate structure and
XOR-array.
CONCLUSION
A low power test pattern generator has been proposed
which consists of a modified low power linear feedback shift
register (LP-LFSR). The seed generated from (LP-LFSR) is
Ex-ORed with the single input changing sequences generated
from gray code generator, which effectively reduces the
switching activities among the test patterns. Thus the proposed
method significantly reduces the power consumption during
testing mode with minimum number of switching activities
using LP-LFSR in place of conventional LFSR in the circuit
used for test pattern generator. From the implementation
results, it is verified that the proposed method gives better
power reduction compared to the exiting method.