14-09-2013, 03:16 PM
Design of multiplexer usingVerilog HDL
Aim:
3. Perform Zero Delay Simulation of multiplexerin Verilog using a Test bench.
4. Synthesize each one of them on two different EDA tools.
Apparatus required:
Electronics Design Automation Tools used:
viii)Xilinx Spartan 3E FPGA +CPLD Board
Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST
ix) Synthesis tool or LeonardoSpectrum Synthesis Tool
x) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
fromSimulation to Implementation to download onto FPGA).
xi) JTAG cable
xii) Adator 5v/4A
Accessing Help
At any time during the tutorial, you can access online help for additional information
about a variety of topics and procedures in the ISE software as well as related tools.
To open Help you may do either of the following:
1. Press to view Help for the specific tool or function that you have selected or
highlighted.-->F1
2. Launch the ISE Help Contents from the Help menu. It contains information about
creating and maintaining your complete design flow in ISE.