11-05-2013, 04:50 PM
Designing and Implementation of SAP-1 Computer using FPGA
Designing and Implementation.doc (Size: 841.5 KB / Downloads: 35)
ABSTRACT
The project is to design and implement SAP-1 Computer using FPGA. The design parameter includes RAM, Instruction Register, Program Counter, Memory Address Register, Controller Sequencer, Accumulator, B Register, OUTPUT Register, Binary Display. The entire design is written in Verilog HDL, which is a hardware description language and is synthesized using Xilinx ISE.