28-08-2014, 09:43 AM
We have undergone training at PUNCOM regarding embedded ARM processor (ARM7TDMI) and Samsung controller (S3C4510B), Samsung S3C4510B has ARM as its CPU and its programming is done in embedded C language. We have studied its architecture, working, instruction set in detail, its programming in embedded C language instead of assembly as its compiler and debugger easily available. We have also studied its interfacing with various peripherals like LED and Keypad and practically performed this.
Basic Embedded System
An embedded system is a computer system designed to perform one or a few dedicated functions often with real-time computing constraints. Embedded systems are controlled by one or more main processing cores that are typically either microcontrollers or digital signal processors (DSP). The key characteristic, however, is being dedicated to handle a particular task, which may require very powerful processors. For example, air traffic control systems may usefully be viewed as embedded, even though they involve mainframe computers and dedicated regional and national networks between airports and radar sites (each radar probably includes one or more embedded systems of its own). Here we use the Arm (Acron Risc Machine) for the embedded system. The ARM architecture supports implementations across a wide range of performance points. It is established as the dominant architecture in many market segments. The architectural simplicity of ARM processors leads to very small implementations, and small implementations mean devices can have very low power consumption. Implementation size, performance, and very low power consumption are key attributes of the ARM architecture It has following features:- • Load/store architecture. • Uniform 16 × 32-bit register file. • Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, "Thumb mode" increased code density. • Mostly single-cycle execution. To compensate for the simpler design, compared with contemporary processors like the Intel 80286 and Motorola 68020, some additional design features were used: • Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch predictor. • Arithmetic instructions alter condition codes only when desired. • 32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address calculations. • Powerful indexed addressing modes. • A link register for fast leaf function calls PRACTICAL APPLICATIONS OF ARM: Embedded USB controllers, HDD controllers, Bluetooth controllers, Networking/WiFi ,Medical scanners Consumer Electronic toys, Low end handheld devices, GPS, MP3 Players, Entry level handsets Automotive Diagnostics, Maintenance, Entertainment, Sensors Industrial Power meters, Circuit breakers, UPS, Brushless motor drive, Factory automation Point of Sale Card readers, ATM, Cash registers, Vending machines COMPANY PROFILE INTRODUCTION Punjab Communications Limited is a leading manufacturer and supplier of telecommunication and IT equipment and solutions in India. Its diverse product range covers voice/data multiplexers, radios, optical/transmission, VSAT, switching equipment, PLCC, power plants, networking, broadband equipment and services. It caters to the growing telecommunications, networking and broadband needs of major organizations and service providers in the country including BSNL, MTNL, railways, power sector, private service operators, corporate etc. In the rapidly developing field of telecommunication. Punjab Communications Limited is taking giant stride to bridges the gap between information processing and mobility, permitting the society to share the benefits of information age. Puncom is one of the India’s premier communication and information technology. It has turn over of about 35 million USD, a significant installed base of telecom solution. In India plus client base, which cover almost every major industry and information segment in India, located most modern city Chandigarh. Puncom has India’s most sophisticated manufacturing and software developing facility. It initially started of as a single product venture, now transferred into multi Product Company, manufacturing a wide range of multiplexing switches and transmission products provide total telecommunication solution to the customer. Puncom also offer a wide range of software package customized for communication products. Puncom mission is to provide technologically superior products and service of high quality on time cost effectively and consistently to achieve investor and most important customer confidence. INFRASTRUCTURE North of New Delhi, located in garden state of Punjab, heart land of Indian entrepreneurship, Puncom was established in July 1981, near the city of Chandigarh. Puncom is largest software development in India. Starting its operation in single rented shed. Now the company has 4 industries spread over land of 17266 square of land. But now puncom has 20,000 plus square of air condition floor space :- • About 100 plus pools of qualified software proffesional. • A diverse hardware platform range including Intel, HP and SUN • Digital expertise on diverse software platform. POTENTIAL VENTURE IN TECHNOLOGY Puncom has mission to continous advance in area of communication and information technology industrial encompassion telecommunicatins, softwares constancy and voice processing. Puncom has india’s most sofasticated manufacturing and software development facilities. For this manufacturing facility is equipped with the latest state of machines like:- • Automated SAD assembly lines. • Multilayer PCB assembly lines. • Wave soldring machine. • Telecom protocol analyzer. About Telecom Division Anticipating the future and understanding its technological crossroads and freeways is a strong PUNCOM trait. Over a period of time, Puncom has conceived, designed and developed a range of highly sophisticated telecom products and during the process equipped with expertise of the higher class. These products are well researched in meeting the needs of the specific target, segment and quickly creating a niche for them. Since the inception in 1981 the telecom division has been the backbone of the company, Puncom today has one of the best manufacturing facilities in India. It has 2,50,000 Sq. ft. of air-conditioned space, full backup power, Automated SMT assembly lines, and wave soldering machines. The linearization of telecom scenario of India provides increased opportunities for PUNCOM with its state of the art technology products and commitments to quality. Puncom's emphasis on total quality management, (TQM) has led to ISO 9002 accreditation and issue of approved inspection status (AIS) by DOT to four of it products. The company has recently embarked upon an aggressive plan to trap the Global market. Puncom also undertakes complete system design, engineering and execution of work on turn key basis in the most effective manner. Company R &D is engaged in the development of new technologies to meet the ever-growing communication need. Besides, a number of new technology tie-ups are at advanced stage. About software design In 1989, Puncom has setup its Information System Design (ISD) foreseeing the convergence of teecom and company technologies. This division has since accumulated valuable skills and experience through implementation of diverse range of information technology projects for the domestic and international market. Puncom ISD has following technologies group to address the current and future needs of the domestic and international software market:- • Internet group • Computer telephony integration group • Network Mangement System (NMS) group • Firmware (DSP’s Microcontroller Assembly) group As an acknowledgement of our premier position on the software maps of punjab, the government of punjab has asked to associate to setting up of software park, to accelerate the growth of software development industry in this part of country. 1.1 Major Activities The company has the following major areas of activities: • Manufacturing • Equipment supply and after sales services • System Design and engineering • Education and turnkey projects involving field maintenance • Survey, Installation commissioning and annual maintenance contacts • Research and Development • Training • Constancy in system and network Planning • Customized software solution Technological Alliances The international business community’s trust on PUNCOM as a valuable partner is amply demonstrated by the long list of technology alliances we have, among these are • Daewoo Corp., South Korea • CIT ALCAREL, France • ECI Telecom, Israel • MICOM, USA • MULTIPOINT, UK • ARE, ITALY • DSC Comm., USA • KOKUSAI Electronics Co., Japan • MATRA Macron Pace, USA • HITRON, Twain • ANT BOSCH, Germany 1.2 1.3 Manufacturing Facilities Puncom has highest precision automatic & semiautomatic machinery and testing instruments. In all functional areas of manufacturing. State of the art technology is combined with the most sophisticated manufacturing processes to make products that are truly world class. These processes have given some of our products a service life of well over a hundred years thereby a setting new standards in product quality. 1.4 1.5 Product Portfolios In its Endeavour to create technologically sound state of art products, the company earlier had collaborations with some of the worlds reputed named in the telecommunications like Granger Associates, USA, ARE Italy and India's very own C-DOT. Recently the company has entered into collaborations with ECI Telecom of Israel for advanced SDH Equipment M/s Dana phone A/s for mobile Communication Equipment and Exactest of Twain for gain equipment. Puncom has strong product portfolios, which cover all the aspects of the telecom market. Few of these are mentioned below: • Switching Products: • Electronics Private Automatics Branch Exchange with direct Inward dialing facility(128/256 parts) • Rural Automatics Exchange(128/256 parts) • Medium Size Digital Exchange(400 to 1500 lines) • Large Size Digital Exchange (1500 to 10,000 lines) • Remote Switching Units(RSU) List of Clients • Department of Telecommunications (DOT)(Indian PTT) • Mahanagar Telephone Nigam Limited (MTNL) • Videsh Sanchar Nigam Limited (VSNL) • Indian Railways • Indian Oil Corporation (IOC) • National Thermal Power Corporation (NTPC) • Steel Authority of India (SAIL) • Bharat Electronics Limited (BEL) • State Electronics Undertakings • Konkan Railways Corporation Limited • Defense Services • Meltron Puncom and its Clients 1.5.1.1.1 The reputation for excellence has extended to selected customers in Europe and Middle East as well. 1.5.1.1.2 The company has today a total of 48 specific clients in India and abroad. 1.5.1.1.3 1.5.1.1.4 PLATFORM AND ENVIRONMENTS DOS, UNIX, SUN OS, Windows 98, Windows NT, LINUX, QNX, Novell Network Databases, Oracle, Sybase (Replication Server, SQL Server and Open Server), MS Access, Clipper Languages C, C++, Assembly, FORTRAN Front Ends, Developer 2000, Power Builder, Visual Basic, Delphi, Visual C++, Case Tool Designer 2000, S-Designer GIS map info, Map Basic Internet Post Script, HTML, JAVA, CGI, Perl Network, TMN are the most commonly used platforms and environments which the Puncom uses for its production. 1.6 Expertise • Application Software • Manufacturing Solution • Financial Institution • Power System • education & Examination Institutions • Process Industry • Sales & Distribution 1.7 KEY STRENGTH • Air-conditioned assembly. • Standby captive power generation: 3 Mw. • Capital equipment: US$11.2 MILLON. • Capability: bit rate -- 2.5 Gbit/s • Frequency -- 40 GHz • Assembly lines: SMT -- two • Conventional -- three • Most peaceful work force • Sales in India: 99%, exports: 1% 1.8 Turn-Key Products • Mobile train radio for railway • Optical fiber and mobile radio for gas authority of India Limited • Microwave/UHF radio for DOT , railway , defense • Optical fiber system for railway • MAX-L digital exchange unto 3.5k capacities for DOT • Circle level maintained contrast • Acceptance testing for GSM mobile network • PLCC & VSS-2100 network for power Grid Corporation of India Ltd. 1.9 Key Activities • Equipment design and Development • Equipment assembly & distribution • Contract assembly • Equipment integration, testing • Field installation • Maintain Contracts • Equipment Repair • Software Design & development 1.10 1.11 Quality Assurance Quality assurance plan is an integral part of each project carried out at Puncom. The quality checks are carried out at all stages of manufacturing i.e. receipt, assembly and testing. Puncom has climatic and vibration testing facilities. In recognition of sterling quality of its products as well as the entire manufacturing processes, Puncom has been awarded ISO 9002 Certification for its ongoing products in multiplexing, switching and radio fields and has been awarded ISO 9001 Certification for its product for software design and development. 1.12 Research & Development The entrepreneurial process of translating business opportunity into results has helped PAL design and capture voice processing in the market. In order to match the present product to the various needs of the customers, research, and development develops new products that meet the needs of the customers. These products are developed in the manner that is highly cost effective and competitive. Company R & D is engaged in development of new technologies to meet the ever-growing communication needs. Besides, a number of new products and tie ups are at an advance stage. 1.13 After sale service & Training The company has established in house repair center in order to provide effective servicing facilities, for ensuring minimum down time. Chapter 1 ARM INTRODUCTION 1.1 INTRODUCTION: The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance for very low power consumption and price. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs. In this meaning of each term of ARM7TDMI is:- A: - Acron R: - RISC (Reduced Instruction Set) M: - Machine 7:- Version T: - Thumb instruction set D: - Debug M:-Long multiply instruction I: - Embedded ICE macro cell 1.2 ARM ARCHITECTURE: The ARM7TDMI processor employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. 1.3 THE THUMB CONCEPT: The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI processor has two instruction sets: • The standard 32-bit ARM set • A 16-bit THUMB set The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the Arm’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. 1.4 THUMB ADVANTAGES: THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB Instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a large address space efficiently. When processing 32-bit data, a 16-bit architecture will take at least two instructions to perform the same task as a single ARM instruction. However, not all the code in a program will process 32-bit data (for example, code that performs character string handling), and some instructions, like Branches, do not process any data at all. If a 16-bit architecture only has 16-bit instructions, and a 32-bit architecture only has 32-bit instructions, then overall the 16-bit architecture will have better code density, and better than one half the performance of the 32-bit architecture. Clearly 32-bit performance comes at the cost of code density. THUMB breaks this constraint by implementing a 16-bit instruction length on a 32-bit architecture, making the processing of 32-bit data efficient with a compact instruction coding. This provides far better performance than a 16-bit architecture, with better code density than a 32-bit architecture. THUMB also has a major advantage over other 32-bit architectures with 16-bit instructions. This is the ability to switch back to full ARM code and execute at full speed. Thus critical loops for applications such as • Fast interrupts • DSP algorithms Can be coded using the full ARM instruction set, and linked with THUMB code. The overhead of switching from THUMB code to ARM code is folded into sub-routine entry time. Various portions of a system can be optimized for speed or for code density by switching between THUMB and ARM execution as appropriate. 1.5 BLOCK,CORE AND FUNCTIONAL DIAGRAMS :- ARM7TDMI PROCESSOR BLOCK DIAGRAM ARM7TDMI MAIN PROCESSOR LOGIC ARM7TDMI PROCESSOR FUNCTIONAL DIAGRAM Chapter 2 PROGRAMMER’S MODEL 2.1 PROCESSOR OPERATING STATES: From the programmer’s point of view, the ARM7TDMI can be in one of two states: • ARM state: This executes 32-bit, word-aligned ARM instructions. • THUMB state: This operates with 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1 to select between alternate half words. 2.2 SWITCHING STATE: • The operating state of the ARM 7TDMI core can be switched between ARM state and THUMB state using BX instruction. • Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state. 2.3 Entering ARM state: Entry into ARM state happens: • On execution of the BX instruction with the state bit clear in the operand register. • On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). 2.4 MEMORY FORMATS: The ARM7TDMI processor views memory as a linear collection of bytes numbered in ascending order from zero. For example: • bytes zero to three hold the first stored word • bytes four to seven hold the second stored word. 2.4.1 BIG ENDIAN FORMAT: In Big Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24. Big endian addresses of bytes within words 1.4.2 LITTLE ENDIAN FORMAT: In Little Endian format, the lowest numbered byte in a word is considered the word’s least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0. Little endian addresses of bytes within words 2.5 INSTRUCTION LENGH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 2.6 DATA TYPES ARM7TDMI supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries. 2.7 OPERATING MODES ARM7TDMI supports seven modes of operation: • User (usr): The normal ARM program execution state • FIQ (fast Interrupt Request): Designed to support a data transfer or channel process • IRQ (Interrupt Request): Used for general-purpose interrupt handling • Supervisor (svc): Protected mode for the operating system • Abort mode (abt): Entered after a data or instruction prefetch abort • System (sys): A privileged user mode for the operating system • Undefined (und): Entered when an undefined instruction is executed mode changes may be made under software control, or may be brought about by external interrupts or exception processing 2.8 REGISTER SET ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six Status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer 2.9 ARM STATE REGISTER SET In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non-User) modes, mode-specific banked registers, Register organization in ARM state shows which registers are available in each mode. The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information. • Register 14 is used as the subroutine link register. This receives a copy of R15 when a Branch and Link (BL) instruction is executed. At all other times it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when Branch and Link instructions are executed within interrupt or exception routines. • By convention R13 is used as the stack pointer. • Register 15 holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC. • Register 16 is the CPSR (Current Program Status Register). This contains condition code flags and the current mode bits. ARM state registers 2.10 THUMB STATE REGISTER SET: The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. THUMB state registers 2.11 RELATIONSHIP BETWEEN ARM AND THUMB STATE: • THUMB state R0-R7 and ARM state R0-R7 are identical • THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical • THUMB state SP maps onto ARM state R13 • THUMB state LR maps onto ARM state R14 • The THUMB state Program Counter maps onto the ARM state Program Counter (R15) Mapping of THUMB state registers onto ARM state registers 2.12 THE PROGRAM STATUS WORD The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These registers • Hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operating mode Program Status Word 2.12.1 Control bits:- • Bit 0-4 (processor mode) These bits determine the processor mode. The modes are listed below:- Bit Configuration M [4:0] • Thumb state (bit 5): This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. • Interrupt mask bits (bit 6-7): The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively 2.12.2 Condition code flag bits: • Overflow flag :V (bit 28): This flag is set if an over flow occur while addition and subtraction. It indicates result is larger than destination. • Carry flag :C (bit 29): If the carry or barrow came out from the arithmetic expression then it set otherwise it reset. • Zero flag :Z (bit 30): If the result of comparison is zero i.e. equal numbers are present then the zero flag is set otherwise it clear. • Negative flag :N (bit 31): The negative flag is set if the result is negative and regarded as two’s compliment of signed integers. Otherwise the flag is cleared if result is positive or zero. 2.12.3 Reserved bits: These bits are reserved for further expansion in future. The user should write his program in such a manner that the bits are unmodified. If the user fails to does this may lead to side-effects on future version of the architecture. 2.13 EXCEPTIONS: Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. 2.13.1 Action on entering an exception: 1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the instruction. 2. Copies the CPSR into the appropriate SPSR 3. Forces the CPSR mode bits to a value which depends on the exception 4. Forces the PC to fetch the next instruction from the relevant exception vector. It may also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state. 2.13.2 Action on leaving an exception: On completion, the exception handler: 1. Moves the Link Register value to the PC. 2. Copies the SPSR back to the CPSR. 3. Clears the interrupt disable flags, if they were set on entry 2.14 Types of exceptions: 2.14.1 FIQ: The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching). It can be disable any time by setting the F bit in the CPSR. FIQ is externally generated by taking the nFIQ input LOW. 2.14.2 IRQ: IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode. IRQ is externally generated by taking the nIRQ input LOW. 2.14.3 ABORT: An abort indicates that the current memory access cannot be completed. It can be signaled by the external ABORT input. ARM7TDMI checks for the abort exception during memory access cycles. There are two types of abort: • Prefetch abort: - If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. • Data abort:- It occurs during an invalid data access. 2.14.4 SOFTWARE INTERRUPT: The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb). MOV PC, R14_svc 2.14.5 UNDEFINED INSTRUCTION: When ARM7TDMI comes across an instruction which it cannot handle, it takes the undefined instruction trap. Example if a coprocessor instruction is executed, the processor waits for any external coprocessor acknowledge that it can execute the instruction. In case no external processor acknowledge, an undefined instruction exception occur. 2.14.6 Reset When the nRESET signal goes LOW, ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. When nRESET goes HIGH again, ARM7TDMI: 1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined. 2. Forces M [4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR’s T bit. 3. Forces the PC to fetch the next instruction from address 0x00. 4. Execution resumes in ARM state. 2.15 Exception vectors The following table shows the exception vector addresses. Address Exception Mode on entry 0x00000000 Reset Supervisor 0x00000004 Undefined instruction Undefined 0x00000008 Software interrupt Supervisor 0x0000000C Abort (prefetch) Abort 0x00000010 Abort (data) Abort 0x00000014 Reserved Reserved 0x00000018 IRQ IRQ 0x0000001C FIQ FIQ Figure 2-8: Vector Table 2.16 Exception Priorities: When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, Software interrupt. Chapter 3 ARM INSTRUCTIONS 3.1 Format summary The ARM instruction set formats are shown below: ARM instruction set format 3.2 ARM INSTRUCTION SET: The ARM instructions are given as: Mnemonic Instruction Action ADC Add with carry Rd := Rn + Op2 + Carry ADD Add Rd := Rn + Op2 AND AND Rd := Rn AND Op2 B Branch R15 := address BIC Bit Clear Rd := Rn AND NOT Op2 BL Branch with Link R14 := R15, R15 := address BX Branch and Exchange R15 := Rn, T bit := Rn[0] CDP Coprocessor Data Processing (Coprocessor-specific) CMN Compare Negative CPSR flags := Rn + Op2 CMP Compare CPSR flags := Rn - Op2 EOR Exclusive OR Rd := (Rn AND NOT Op2) OR (op2 AND NOT Rn) LDC Load coprocessor from Memory Coprocessor load LDM Load multiple registers Stack manipulation (Pop) LDR Load register from memory Rd := (address) MLA Multiply Accumulate Rd := (Rm * Rs) + Rn MOV Move register or constant Rd : = Op2 MRS Move PSR status/flags to register Rn := PSR MSR Move register to PSR status/flags PSR := Rm MUL Multiply Rd := Rm * Rs MVN Move negative register Rd := 0xFF EOR Op2 ORR OR Rd := Rn OR Op2 RSB Reverse Subtract Rd := Op2 - Rn RSC Reverse Subtract with Carry Rd := Op2 – Rn - 1 + Carry SBC Subtract with Carry Rd := Rn - Op2 - 1 + Carry STM Store Multiple Stack manipulation (Push) STR Store register to memory <address> := Rd SUB Subtract Rd := Rn - Op2 SWP Swap register with memory Rd := [Rn], [Rn] := Rm TEQ Test bitwise equality CPSR flags := Rn EOR Op2 TST Test bits CPSR flags := Rn AND Op2 Figure 3-2: List of Instructions 3.3 THE CONDITION FIELD: In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction’s condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction’s mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which means the Branch will only be taken if the Z flag is set. Some of condition codes are:- Suffix Flags Meaning EQ Z set equal NE Z clear not equal CS C set unsigned higher or same CC C clear unsigned lower MI N set negative PL N clear positive or zero VS V set overflow VC V clear no overflow HI C set and Z clear unsigned higher LS C clear or Z set unsigned lower or same GE N equals V greater or equal LT N not equal to V less than GT Z clear AND (N equals V) greater than LE Z set OR (N not equal to V) less than or equal AL (ignored) always List of Conditions 3.4 Branch and Exchange (BX): This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn [0] determines whether the instruction stream will be decoded as ARM or THUMB instructions. Branch and Exchange Format Examples MOV R0, # 57h ; Generate branch target address and set bit 0 high BX R0 ; Branch and change to THUMB state 3.5 Branch and Branch with Link (B, BL): Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC. To return from a routine called by Branch with Link use MOV PC, R14 if the link register is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn. Branch and Link Format Assembler syntax Items in {} are optional. Items in <> must be present. B {L} {cond} <expression> {L} is used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the instruction. {Cond} is a two-character mnemonic. If absent then AL (Always) will be used. <Expression> is the destination. The assembler calculates the offset Examples BLEQ sub ; Branch to sub when condition true . . Sub: MOV R0, #64h ; Branch destination 3.6 Data Processing The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction. Data processing instructions 3.7 Logical Shifts When the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. A logical shift left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class. Logical shift left With LSL #5 • Note: LSL #0 is a special case, where the shifter carries out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand. A logical shift right (LSR) is similar, but the contents of Rm are moved to Right positions in the result. Logical shift Right With LSL #5 3.8 Arithmetic Shift: An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm instead of zeros. The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to the value of bit 31 of Rm. Figure 5-9: Arithmetic shift Right with ASR #5 3.9 Rotate: Rotate right (ROR) operations reuse the bits which in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm Rotate Right with ROR #5 Rotate Right Extended with RRX #5 3.10 TEQ, TST, CMP & CMN: Its working is shown in above table. It has: Assembler syntax 1. MOV, MVN (single operand instructions.) <Opcode> {cond} {S} Rd, <Op2> 2. CMP, CMN, TEQ, TST (instructions which do not produce a result.) <Opcode> {cond} Rn, <Op2> 3. AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, ORR, BIC <Opcode> {cond} {S} Rd, Rn, <Op2> Where: <Op2> is Rm {<shift>} {Cond} is a two-character condition mnemonic. {S} set condition codes if S present (implied for CMP, CMN, TEQ, and TST). Rd, Rn and Rm are expressions evaluating to a register number. <Shift> is <shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with extend). <Shiftname>s are: ASL, LSL, LSR, ASR, and ROR. (ASL is a synonym for LSL they assemble to the same code.) Examples ADDEQ R2, R4, R5 ; If the Z flag is set makes R2:=R4+R5 TEQS R4, #3 ; test R4 for equality with 3. (The S is in fact redundant as the assembler inserts it automatically.) SUB R4, R5, R7, LSR R2 ; Logical right shift R7 by the number in the bottom byte of R2, subtracts result from R5, and put the answer into R4. MOV PC, R14 ; Return from subroutine. 3.11 MRS and MSR (PSR Transfer): These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the CPSR or SPSR_<mode> to be moved to a general register. The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR_<mode> register. The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags (N,Z,C and V) of CPSR or SPSR_<mode> without affecting the control bits. In this case, the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR. Assembler syntax 1. MRS - transfer PSR contents to a register MRS {cond} Rd, <psr> 2. MSR - transfer register contents to PSR MSR {cond} <psr>, Rm Where: {Cond} two-character condition mnemonic Rd and Rm are expressions evaluating to a register number other than R15 <Psr> is CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are Synonyms as are SPSR and SPSR_all) Examples MSR CPSR, Rm ; CPSR [31:28] <- Rm [31:28] MSR CPSR_flg, #0xA0000000 ; CPSR [31:28] <- 0xA (set N, C; clear Z, V) MRS Rd, CPSR ; Rd [31:0] <- CPSR [31:0] 3.12 Multiply and Multiply-Accumulate (MUL, MLA) The multiply form of the instruction gives Rd =Rm*Rs. Rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd =Rm*Rs+Rn, which can save an explicit ADD instruction in some circumstances. Multiply instructions Assembler syntax 1. MUL {cond} {S} Rd, Rm, Rs 2. MLA {cond} {S} Rd, Rm, Rs, Rn Where: {Cond} two-character condition mnemonic {S} set condition codes if S present Rd, Rm, Rs and Rn are expressions evaluating to a register number other than R15. Examples MUL R1, R2, R3 ; R1:=R2*R3 MLAEQS R1, R2, R3, R4 ; Conditionally R1:=R2*R3+R4, setting condition ; codes. 3.13 Multiply Long and Multiply-Accumulate Long (MULL, MLAL): The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results The multiply forms (UMULL and SMULL) take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi, RdLo := Rm * Rs. The lower 32 bits of the 64 bit results are written to RdLo, the upper 32 bits of the result are written to RdHi. The multiply-accumulate forms (UMLAL and SMLAL) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi,RdLo := Rm*Rs + RdHi,RdLo. The lower 32 bits of the 64 bit number to add is read from RdLo. The upper 32 bits of the 64 bit number to add is read from RdHi. The lower 32 bits of the 64 bit result are written to RdLo. The upper 32 bits of the 64 bit result are written to RdHi. Assembler syntax 1. MULL {cond} {S} RdLo, RdHi, Rm, Rs 1. MULAL {cond} {S} RdLo, RdHi, Rm, Rs Where: {Cond} two-character condition mnemonic {S} set condition codes if S present RdLo, RdHi, Rm, Rs are expressions evaluating to a register number other than R15. Examples UMULL R1, R4, R2, R3 ; R4, R1:=R2*R3 UMLALS R1, R5, R2, R3 ; R5, R1:=R2*R3+R5, R1 also setting condition ; codes 3.14 Single Data Transfer (LDR, STR) The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required. Single data transfer instructions Assembler syntax <LDR|STR> {cond} <B|H> {T} Rd, <Address> Where: LDR load from memory into a register STR store from a register into memory {Cond} two-character condition mnemonic {B} if B is present then byte transfer, otherwise word transfer {H} Transfer halfword quantity {T} if T is present the W bit will be set in a post-indexed instruction. T is not allowed when a pre-indexed addressing mode is specified or implied. Rd is an expression evaluating to a valid register number. <Address> can be: 1. An expression which generates an address: <Expression> The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated. 2 A pre-indexed addressing specification: [Rn] Offset of zero [Rn, <#expression>]{!} Offset of <expression> bytes [Rn, {+/-}Rm{,<shift>}]{!} Offset of +/- contents of index register, shifted by <shift> 3 A post-indexed addressing specification: [Rn],<#expression> offset of <expression> bytes [Rn],{+/-}Rm{,<shift>} offset of +/- contents of index register, shifted as by <shift>. <Shift> general shift operation (see data processing instructions) but you cannot specify the shift amount by a register. {!} Writes back the base register (set the W bit) if! Is present Examples STR R1, [R2, R4]! ; Store R1 at R2+R4 (both of which are registers) ; and write back address to R2. STR R1, [R2], R4 ; Store R1 at R2 and write back R2+R4 to R2 LDR R1, [R2, #16] ; Load R1 from contents of R2+16, but don't write back. LDR R1, [R2, R3, LSL#2] ; Load R1 from contents of R2+R3*4 LDREQ, [R6, #5] ; conditionally load byte at R6+5 into R1 bits ; 0 to 7, filling bits 8 to 31 with zeros 3.15 Block Data Transfer (LDM, STM) Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory. Post-increment addressing Pre-increment addressing Assembler syntax <LDM|STM> {cond} <FD|ED|FA|EA|IA|IB|DA|DB> Rn {!}, <Rlist> Where: {Cond} two character condition mnemonic Rn is an expression evaluating to a valid register number <Rlist> is a list of registers and register ranges enclosed in {} (e.g. {R0, R2- R7, and R10}). {!} if present requests write-back (W=1), otherwise W=0 Examples LDMFD SP! , {R0, R1, R2} ; Unstack 3 registers. STMIA R0, {R0-R15} ; Save all registers. LDMFD SP! , {R15} ; R15 <- (SP), CPSR unchanged 3.16 Single Data Swap (SWP) The data swap instruction is used to swap a byte or word quantity between a register and external memory. This instruction is implemented as a memory read followed by a memory write which are “locked” together (the processor cannot be interrupted until both operations have completed, and memory manager is warned to treat them as inseparable). Swap Instruction Format The swap address is determined by the contents of the base register (Rn). The processor first reads the contents of the swap address. Then it writes the contents of the source register (Rm) to the swap address, and stores the old memory contents in the destination register (Rd). The same register may be specified as both the source and destination. Assembler syntax <SWP> {cond} {B} Rd, Rm, [Rn] Where: {Cond} two-character condition mnemonic {B} if B is present then byte transfer, otherwise word transfer Rd, Rm, Rn are expressions evaluating to valid register numbers Examples SWP R0, R1, [R2] ; Load R0 with the word addressed by R2, and store R1 at R2 SWPB R2, R3, [R4] ; Load R2 with the byte addressed by R4, and store bits 0 to 7 of R3 at R4 SWPEQ R0, R0, [R1] ; conditionally swap the contents of the word addressed by R1 with R0. Chapter 4 Memory Interface 4.1 Overview ARM7TDMI’s memory interface consists of the following basic elements: • 32-bit address bus This specifies to memory the location to be used for the transfer. • 32-bit data bus Instructions and data are transferred across this bus. Data may be word, halfword or byte wide in size. ARM7TDMI includes a bidirectional data bus, D[31:0], plus separate unidirectional data busses, DIN[31:0] and DOUT[31:0]. Most of the text in this chapter describes the bus behaviors assuming that the bidirectional is in use. However, the behavior applies equally to the unidirectional busses. • Control signals These specify, for example, the size of the data to be transferred, and the direction of the transfer together with providing privileged information. This collection of signals allows ARM7TDMI to be simply interfaced to DRAM, SRAM and ROM. 4.2 Cycle Types All memory transfer cycles can be placed in one of four categories: 4.2.1 Non-sequential cycle: ARM7TDMI requests a transfer to or from an address which is unrelated to the address used in the preceding cycle. 4.2.2 Sequential cycle: ARM7TDMI requests a transfer to or from an address which is either the same as the address in the preceding cycle, or is one word or halfword after the preceding address. 4.2.3 Internal cycle: ARM7TDMI does not require a transfer, as it is performing an internal function and no useful prefetching can be performed at the same time. 4.2.4 Coprocessor registers transfer: ARM7TDMI wishes to use the data bus to communicate with a coprocessor, but does not require any action by the memory system. These four classes are distinguishable to the memory system by inspection of the nMREQ and SEQ control lines (see Table: Memory cycle types). Figure 6-1: Memory cycle types Figure: ARM memory cycle timing shows the pipelining of the control signals, and suggests how the DRAM address strobes (nRAS and nCAS) might be timed to use page mode for S-cycles. ARM memory cycle timing When an S-cycle follows an N-cycle, the address will always be one word or halfword greater than the address used in the N-cycle. This address (marked “a” in the above diagram) should be checked to ensure that it is not the last in the DRAM page before the memory system commits to the S-cycle. If it is at the page end, the S-cycle cannot be performed in page mode and the memory system will have to perform a full access. The processor clock must be stretched to match the full access. When an S-cycle follows an I-cycle, the address will be the same as that used in the I-cycle 4.3 Data Transfer Size In an ARM7TDMI system, words, halfwords or bytes may be transferred between the processor and the memory. The size of the transaction taking place is determined by the MAS [1:0] pins. These are encoded as follows: 00 Byte 01 halfword 10 word 11 reserved The processor always produces a byte address, but instructions are either word (4 bytes) or halfwords (2 bytes), and data can be any size. Note that when word instructions are fetched from memory, A[1:0] are undefined and when halfword instructions are fetched, A[0] is undefined. 4.4 Instruction Fetch ARM7TDMI will perform 32- or 16-bit instruction fetches depending on whether the processor is in ARM or THUMB state. The processor state may be determined externally by the value of the TBIT signal. When this is LOW, the processor is in ARM state and 32-bit instructions are fetched. When TBIT is HIGH, the processor is in THUMB state and 16-bit instructions are fetched. The size of the data being fetched is also indicated on the MAS [1:0] bits, as described above. When the processor is in ARM state, 32-bit instructions are fetched on D[31:0]. When the processor is in THUMB state, 16-bit instructions are fetched from either the upper, D[31:16], or the lower D[15:0] half of the bus. This is determined by the endianism of the memory system, as configured by the BIGEND input, and the state of A[1]. Table: Endianism effect on instruction position shows which half of the data bus is sampled in the different configurations. Endianism effect on instruction position When a 16-bit instruction is fetched, ARM7TDMI ignores the unused half of the data bus. Table: Endianism effect on instruction position describes instructions fetched from the bidirectional data bus (i.e. BUSEN is LOW). When the unidirectional data busses are in use (i.e. BUSEN is HIGH), data will be fetched from the corresponding half of the DIN[31:0] bus. 4.5 Locked Operations The ARM instruction set of ARM7TDMI includes a data swap (SWP) instruction that allows the contents of a memory location to be swapped with the contents of a processor register. This instruction is implemented as an uninterruptible pair of accesses; the first access reads the contents of the memory, and the second writes the register data to the memory. These accesses must be treated as a contiguous operation by the memory controller to prevent another device from changing the affected memory location before the swap is completed. ARM7TDMI drives the LOCK signal HIGH for the duration of the swap operation to warn the memory controller not to give the memory to another device. When BUSEN is LOW, the buffer between DIN[31:0] and D[31:0] is disabled. Any data presented on DIN[31:0] is ignored. Also, when BUSEN is low, the value on DOUT[31:0] is forced to 0x00000000. Typically, the unidirectional busses would be used internally in ASIC embedded applications. Externally, most systems still require a bidirectional data bus to interface to external memory, shows how the unidirectional busses may be joined up at the pads of an ASIC to connect to an external bidirectional bus. External connection of unidirectional busses 4.6 The bidirectional data bus ARM7TDMI has a bidirectional data bus, D[31:0]. Most of the time, the ARM reads from memory and so this bus is configured to input. During write cycles however, the ARM7TDMI must output data. During phase 2 of the previous cycle, the signal nRW is driven HIGH to indicate a write cycle. During the actual cycle, nENOUT is driven LOW to indicate that the ARM7TDMI is driving D[31:0] as an output. This exists in ARM7TDMI for controlling exactly when the external bus is driven out Chapter 5 COPROCESSOR INTERFACE 5.1 Overview The functionality of the ARM7TDMI instruction set may be extended by the addition of up to 16 external coprocessors. Adding the coprocessor will then increase the system performance in a software compatible way. Note that some coprocessor numbers have already been assigned. Contact ARM Ltd for up-to-date information 5.2 Interface Signals Three dedicated signals control the coprocessor interface, nCPI(Co-processor interrupt), CPA(Co-processor absent) and CPB(Co-processor busy). The CPA and CPB inputs should be driven HIGH except when they are being used for handshaking. 5.3 Coprocessor present/absent ARM7TDMI takes nCPI LOW whenever it starts to execute a coprocessor instruction. (This will not happen if the instruction fails to be executed because of the condition codes.) • Each coprocessor will have a copy of the instruction, and can inspect the CP# field to see which coprocessor it is for. • Every coprocessor in a system must have a unique number and if that number matches the contents of the CP# field the coprocessor should drive the CPA (coprocessor absent) line LOW. • If no coprocessor has a number which matches the CP# field, CPA and CPB will remain HIGH, and ARM7TDMI will take the undefined instruction trap. • Otherwise ARM7TDMI observes the CPA line going LOW, and waits until the coprocessor is not busy 5.4 Busy-waiting If CPA goes LOW, ARM7TDMI will watch the CPB (coprocessor busy) line. Only the coprocessor which is driving CPA LOW is allowed to drive CPB LOW, and it should do so when it is ready to complete the instruction. ARM7TDMI will busy-wait while CPB is HIGH, unless an enabled interrupt occurs, in which case it will break off from the coprocessor handshake to process the interrupt. Normally ARM7TDMI will return from processing the interrupt to retry the coprocessor instruction. When CPB goes LOW, the instruction continues to completion. This will involve data transfers taking place between the coprocessor and either ARM7TDMI or memory, except in the case of coprocessor data operations which complete immediately the coprocessor ceases to be busy. All three interface signals are sampled by both ARM7TDMI and the coprocessor(s) on the rising edge of MCLK. If all three are LOW, the instruction is committed to execution, and if transfers are involved they will start on the next cycle. If nCPI has gone HIGH after being LOW, and before the instruction is committed, ARM7TDMI has broken off from the busy-wait state to service an interrupt. The instruction may be restarted later, but other coprocessor instructions may come sooner, and the instruction should be discarded 5.5 Data transfer cycles Once the coprocessor has gone not-busy in a data transfer instruction, it must supply or accept data at the ARM7TDMI bus rate (defined by MCLK). It can deduce the direction of transfer by inspection of the L bit in the instruction. The coprocessor is responsible for determining the number of words to be transferred; ARM7TDMI will continue to increment the address by one word per transfer until the coprocessor tells it to stop. The termination condition is indicated by the coprocessor driving CPA and CPB HIGH. There is no limit in principle to the number of words which one coprocessor data transfer can move, but by convention no coprocessor should allow more than 16 words in one instruction. More than this would worsen the worst case ARM7TDMI interrupt latency, as the instruction is not interruptible once the transfers have commenced. At 16 words, this instruction is comparable with a block transfer of 16 registers, and therefore does not affect the worst case latency. 5.6 Undefined Instructions Undefined instructions are treated by ARM7TDMI as coprocessor instructions. All coprocessors must be absent (ie CPA and CPB must be HIGH) when an undefined instruction is presented. ARM7TDMI will then take the undefined instruction trap. Note that the coprocessor need only look at bit 27 of the instruction to differentiate undefined instructions (which all have 0 in bit 27) from coprocessor instructions (which all have 1 in bit 27) Note that when in THUMB state, coprocessor instructions are not supported but undefined instructions are. Thus, all coprocessors must monitor the state of the TBIT output from ARM7TDMI. When ARM7TDMI is in THUMB state, coprocessors must appear absent (i.e. they must drive CPA and CPB HIGH) and the instructions seen on the data bus must be ignored. In this way, coprocessors will not erroneously execute THUMB instructions, and all undefined instructions will be handled correctly. Chapter 6 SAMSUNG S3C4510B MICROCONTROLLER 6.1 Overview Samsung's S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in managed communication hubs and routers. The S3C4510B is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. The S3C4510B offers a configurable 8K-byte unified cache/SRAM and Ethernet controller which reduces total system cost. Most of the on-chip function blocks have been desi