25-08-2017, 09:32 PM
FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications
1FPGA-Based Reconfigurable .pdf (Size: 630.86 KB / Downloads: 32)
Abstract
Advances in distributed system technology have
enabled new computation paradigms such as Grid, Cloud, and
Internet computing. Due to the logical and physical
organization of these paradigms, portable and embedded
computing devices are being developed and naturally
becoming an integral part of these systems. In addition to
stringent area and power requirements, design constraints
such as time-to-market and competitive margin pose serious
challenges to embedded hardware designers. One of the most
promising avenues to overcome these challenges is
reconfigurable hardware. In this work, FPGA-based
reconfigurable hardware is examined. As a case study,
Principal Component Analysis (PCA), the classical technique
to reduce the dimensionality of data and to extract dominant
features, is designed and implemented as hardware on FPGA
to be reconfigured dynamically during execution. Using part of
a handwriting analysis application together with a benchmark
dataset, experiments are performed to evaluate the feasibility,
efficiency, and flexibility of reconfigurable hardware.
INTRODUCTION
Data mining is an important research area as many
applications in various domains can make use of it to sieve
through large volumes of data to discover useful patterns and
valuable knowledge. Many of the data mining algorithms
require complex computations and processing speed is a
major concern. One can employ newer computation
paradigm such as cloud and grid to leverage the power of
parallel and distributed computing. However, there exist
many applications, such as hand-held, portable, embedded
devices, that are more suitable to be processed in traditional
computing environment.
DESIGN APPROACH AND DEVELOPMENT PLTFORM
For all our experiments, both software and hardware
versions (static reconfigurable hardware (SRH) and dynamic
reconfigurable hardware (DRH)) of the various computations
are implemented using a hierarchical platform-based design
approach to facilitate component reuse at different levels of
abstraction. As depicted in Fig. 1, our design consists of
different abstraction levels, where higher-level functions
utilize lower-level sub-functions and operators.
Process of Reconfiguration
Reconfigurable hardware designs, such as FPGA-based
designs, are typically written in a hardware description
language (HDL) such as Verilog or VHDL. This abstract
design has to undergo series of steps [7,8] to fit into FPGA’s
available logic. The first step is logic synthesis, which
converts high-level logic constructs and behavioural code
into logic gates. The second step, technology mapping,
separates the gates into groupings that matches the FPGA’s
logic resources (i.e., generates net list). The next two steps
are placement and routing, where placement assigns the logic
groupings the specific logic blocks and routing determines
the interconnect resources that will carry the user’s signals.
The final step is bitstream generation, which creates a
“configuration bitstream”.
Dynamic Partial Reconfigurable Hardware for PCA
In this section, a reconfigurable hardware solution for
PCA is introduced using partial reconfiguration. This
hardware design can be dynamically reconfigured to
accommodate two stages of the PCA computation process.
Initially, we investigated different stages of PCA
[16,17,18], and then considered each stage as individual
operations, and provided hardware support for each stage
separately. In this paper, we are introducing a reconfigurable
hardware solution for the first two stages of the PCA
computation: Mean and Covariance Matrix computations.
Our hardware design can be reconfigured partially and
dynamically from one stage to another, in order to perform
these two operations on the same area of the chip.
DISCUSSION AND CONCLUSION
The results shown in our experiments are encouraging
and show great potential in implementing PCA using a
reconfigurable platform. Trading off speed as compared to
parallel computation, complex processing can indeed be
implemented in reconfigurable hardware for embedded and
portable applications. Currently, we are investigating formal
design approaches and methodologies in using
reconfigurable FPGAs.