06-05-2013, 04:38 PM
Fault Modeling
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Relationship Between Single and
Multiple Faults
Irredundant two-level circuit
¨ Complete test for SSF also detects all MSF
[Kohavi and Kohavi, 1972]
Fanout-free circuit
¨ Any complete test for SSF detects all double
and triple faults [Hayes, 1971]
Internal fanout-free circuit (fanout > 1 on
primary inputs only)
¨ Any complete test for SSF detects greater than
98% of MSF with 5 or fewer faults [Agarwal and
Fung, 1981]
IDDQ Faults
Advantages
¨ Covers most bridge faults
¨ Covers some open faults
¨ Higher defect coverage than stuck-at tests
Disadvantages
¨ Circuit must be designed with low IDDQ
¨ Test application slow
¨ Some open faults escape IDDQ tests
¨ Some timing faults escape IDDQ tests
¨ Current threshold has to be empirically established
Delay Faults
Model defects that affect the circuit timing (resistive shorts
and opens)
Transition faults and Gate Delay faults
¨ Models slow-to-rise or slow-to-fall transition on logic gate
Path Delay Faults (robust and non-robust testing):
¨ Models slow-to-rise or slow-to-fall transition on some
path(s) from primary input to primary outputs
s Advantage: covers transition and gate delay faults
s Disadvantages: test application in non-scan sequential
circuits cannot be done at-speed. Number of paths may be
(exponentially) large
Method of Structural Equivalence
Introduce fault f in the network N and reduce
the structure to S(Nf).
Similarly obtain the structure S(Ng).
If S(Nf) = S(Ng) then clearly function Nf = Ng
and therefore f and g are equivalent faults.
Structural equivalence implies functional
equivalence.