05-04-2012, 12:13 PM
FinFET Scaling to 10nm Gate Length
10.1.1.136.3757.pdf (Size: 814.56 KB / Downloads: 135)
Introduction
Si CMOS has been the main stream IC fabrication
technology for three decades. In the last few years, the
industry has witnessed a striking progress in downsizing the
planar CMOS. Despite many fabrication challenges, 15nm
physical gate length bulk MOSFETs have been recently
demonstrated. However, scaling planar CMOS to 10nmand-
below would be exceptionally difficult, if not
completely impossible, due to electrostatics, excessive
leakages, mobility degradation, and many realistic
fabrication issues. Particularly, control of leakage (hence
power) in a nanoscale transistor would be critical to highperformance
chips such as microprocessors.
Fabrication
the schematic diagram of the
double-gate FinFET fabrication process. Figure 1 (g)-(h)
are the top- and tilted-view SEM of a FinFET in the middle
of fabrication (after gate etching). Figure 2 is the layout
design of a FinFET with single-fin structure. Multiple-fin
devices were also fabricated in this experiment. A major
distinction between a FinFET and a traditional planar FET
is an appreciably narrowed active region (fin). Reduction of
the fin width (i.e., body thickness), Tfin, is important to the
scaling of double-gate FinFET. In addition, the overlay of
the gate to the active layer should be effectively controlled
to reduce the transistor performance variation.
Device Characteristics
A. Scaling Performance
Figure 3 is the TEM of a FinFET with a 10nm-long
poly-Si gate. NiSi was formed on top of the poly-Si gate
electrode. Figure 4 is the TEM of a narrow Si fin etched
from the SOI wafer. Figure 5 is the Id-Vd characteristics of
the 10nm gate length CMOS FinFETs. The drive currents
are 446μA/μm for n-channel FinFET and 356μA/μm for pchannel
FinFET, both measured at a gate over-drive of 1V
and a Vdd of 1.2V. All the currents are normalized by two
times the fin height (i.e., the total channel width of a
double-gate device).
Summary
Double-gate CMOS FinFETs were fabricated with the
smallest physical gate length ever reported. With the
demonstrated scalability and potential performance benefit
(under the penalty of adding some fabrication complexity to
the existing planar process), the FinFET would be a strong
competitor or successor to classical CMOS. While a few
non-show-stopper issues (e.g., gate material engineering
and parasitics reduction) need to be addressed, the FinFET
is promising for the extremely scaled CMOS in which the
packing density, scalability, performance, and power
dissipation would be among the vital challenges.