04-07-2013, 04:23 PM
CMOS Switched-Op-Amp-Based Sample-and-Hold Circuit
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Abstract
This paper presents a sample-and-hold design that
is based on a switched-op-amp topology. Charge injection errors
are greatly reduced by turning off transistors in the saturation
region instead of the triode region as is the case for traditional
MOS switches. The remaining clock feedthrough error is mostly
signal-independent and is cancelled out by a pseudodifferential
topology. Switched-op-amps are designed and fabricated in a
2-m CMOS technology. The measurement results show that the
harmonics are at least 78 dB below the signal level. Both the
measurement results from fabricated IC’s and simulation results
suggest the potential benefits of this approach in comparison to
traditional switched-capacitor circuits.
INTRODUCTION
SAMPLE-AND-HOLD (S/H) circuits are important
building blocks in data-converter systems. Traditional
switched-capacitor (SC) techniques take advantage of the
excellent properties of on-chip capacitors and MOS switches
and permit the realization of numerous analog sampled-data
circuits. Unfortunately, channel charge injection and clock
feedthrough are the major sources of errors when the switch is
turned off. Though many switching techniques [1]–[3] and circuit
topologies [4]–[7] have been proposed and developed, the
nonlinearity caused by charge injection and clock feedthrough
still limits circuit performance, particularly in high-resolution
data converters.
SWITCHED-OP-AMP-BASED SAMPLE-AND-HOLD CIRCUITS
In this section, we introduce our SOP-based S/H design,
where our idea of turning off devices in the saturation region
is implemented. First, we build a simplified model for our
design and discuss the impact of circuit nonidealities. We then
show our S/H circuit design and discuss its advantages over
traditional SC S/H circuits.
Model and Simulation Results
Fig. 3 shows the block diagram of an SOP-based S/H. During
the sample mode, the SOP behaves just like a regular op-amp.
If the op-amp is assumed to be ideal, then during the sample
mode, the S/H output follows the input. In the hold mode, the
SOP is shut off and node is held at high impedance. So the
charge on is preserved throughout the hold mode. The output
buffer is operational during both the hold and sample modes and
provides the voltage sampled on the capacitor at the output.
To further reduce the signal-independent error caused by
clock feedthrough, we use a pseudodifferential topology by
duplicating the circuit shown in Fig. 3. If the two circuit halves
are matched, then even this offset is cancelled out.
MEASUREMENT RESULTS
Two of our example designs were fabricated in a 2-mCMOS
process. Circuit designs with transistors in both strong inversion
and weak inversion were generated. The die photograph
is shown in Fig. 8. The top circuit is an S/H capable of operating
at 2 V of power supply, and its devices are operated in the
weak inversion. The bottom one is an S/H using folded-cascode
op-amps, as shown in Fig. 7. In this section, we provide measurement
results that were used to verify our design. As will be
seen, the measurement results are in good agreement with our
theoretical analysis and computer simulations.
CONCLUSIONS
In this paper, a novel S/H design was introduced. The
switches are turned off in the saturation region rather than in
the triode region as in traditional MOS switches. Hence, the
channel charge injection error is completely removed. The remaining
signal-dependent clock feedthrough error is cancelled
out by a pseudodifferential structure. In applications where
the signal-independent offset is not important, a single-ended
version of the S/H can be used. Simulation and measurement
results show good agreement with our analysis.
Since our research motivation was for extremely low-power
medical applications, our designs concentrated on signals at low
frequencies. However, the basic idea can be extended to highfrequency
applications. Since our design does not suffer from
charge injection error, which is input signal-dependent, we expect
to achieve the same linearity even with a smaller load capacitance.
Thus high-speed operation can be achieved.