20-09-2009, 03:52 PM
HYPER TRANSPORT TECHNOLOGY
1.ABSTRACT
The hyper transport protocol defines a high-performance and scalable interconnect between CPU, memory, and I/O devices. Conceptually, the architecture of the Hyper Transport I/O link can be mapped into five different layers, which structure is similar to the Open System Interconnection (OSI) reference model. In Hyper Transport technology: 1. The physical layer defines the physical and electrical characteristics of the protocol. This layer interfaces to the physical world and includes data, control, and clock lines 2. The data link layer includes the initialization and configuration sequence, periodic Cyclic redundancy check (CRC), disconnect/reconnect sequence, information packet for flow control and error management, and double word framing for other packets. 3. The protocol layer includes the commands, the virtual channels in which they run, and the ordering rules that govern their flow.
2.INTRODUCTION
The demand for faster processors, memory and I/O is a familiar refrain in market applications ranging from personal computers and servers to networking systems and from video games to office automation equipment. Once information is digitized, the speed at which it is processed becomes the foremost determinate of product success. Faster system speed leads to faster processing. Faster processing leads to faster system performance. Faster system performance results in greater success in the marketplace. This obvious logic has led a generation of processor and memory designers to focus on one overriding objective “ squeezing more speed from processors and memory devices.Processor designers have responded with faster clock rates and super pipelined architectures that use level 1 and level 2 caches to feed faster execution units even faster. Memory designers have responded with dual data rate memories that allow data access on both the leading and trailing clock edges doubling data access. I/O developers haveresponded by designing faster and wider I/O channels and introducing new protocols to meet anticipated I/O needs. Today, processors hit the market with 2+ GHz clock rates, memory devices provide sub5 ns access times and standard I/O buses are 32- and 64-bit wide, with new higher speed protocols on the horizon. Increased processor speeds, faster memories, and wider I/O channels are not always practical answers to the need for speed. The main problem is integration of more and faster system elements. Faster execution units, faster memories and wider, faster I/O buses lead to crowding of more high-speed signal lines onto the physical printed circuit board. One aspect of the integration problem is the physical problems posed by speed. Faster signal speeds lead to manufacturing problems due to loss of signal integrity and greater susceptibility to noise. Very high-speed digital signals tend to become high frequency radio waves exhibiting the same problematic characteristics of high-frequency analog signals. This wreaks havoc on printed circuit board™s manufactured using standard, lowcost materials and technologies. Signal integrity problems caused by signal crosstalk, signal and clock skew and signal reflections increase dramatically as clock speed increases. The other aspect of the Hyper transport Technology integration problem is the I/O bottleneck that develops when multiple high-speed execution units are combined for greater performance. While faster execution units relieve processor performance bottlenecks, the bottleneck moves to the I/O links. Now more data sits idling, waiting for the processor and I/O buses to clear and movement of large amounts of data from one subsystem to another slows down the overall system performance ratings.
3.CAUSES LEADING TO DEVELOPMENT OF HYPERTRANSPORT TECHNOLOGY
ž h I/O Band width problem žh High pint count žh High power consumption While microprocessor performance continues to double every eighteen months, the Performance of the I/O bus architecture has lagged, doubling in performance approximately every three years, as illustrated below
. This I/O bottleneck constrains system performance, resulting in diminished actual Performance gains as the processor and memory subsystems evolve. Over the past 20 years, a number of legacy buses, such as ISA, VL-Bus, AGP, LPC, PCI- 32/33, and PCI-X, have emerged that must be bridged together to support a varying array of devices. Servers and workstations require multiple high-speed buses, including PCI-64/66. AGP Pro, and SNA buses like InfiniBand. The hodge-podge of buses increases system complexity, adds many transistors devoted to bus arbitration and bridge logic, while delivering less than optimal performance. A number of new technologies are responsible for the increasing demand for additional bandwidth. High-resolution, texture-mapped 3D graphics and high-definition streaming video are escalating bandwidth needs between CPUs and graphics processors. Technologies like high-speed networking (Gigabit Ethernet, InfiniBand, etc.) and wireless communications (Bluetooth) are allowing more devices to exchange growing amounts of data at rapidly increasing speeds. Software technologies are evolving, resulting in breakthrough methods of utilizing multiple system processors. As processor speeds rise, so will the need for very fast, high-volume inter- processor data traffic. While these new technologies quickly exceed the capabilities of today™s PCI bus, existing interface functions like MP3 audio, v.90 modems, USB, 1394, and 10/100Ethernet are left to compete for the remaining bandwidth. These functions are now commonly integrated into core logic products. Higher integration is increasing the number of pins needed to bring these multiple buses into and out of the chip packages. Nearly all of these existing buses are single ended, requiring additional power and ground pins to provide sufficient current return paths. High pin counts increase RF radiation, which makes it difficult for system designers to meet FCC and VDE requirements. Reducing pin count helps system designers to reduce power consumption and meet thermal requirements. In response to these problems, AMD began developing the Hyper Transport„¢ I/O link architecture in 1997. Hyper Transport technology has been designed to provide system architects with significantly more bandwidth, lowlatency responses,lower pin counts, compatibility with legacy PC buses, extensibility to new SNA buses, and transparency to operating system software, with little impact on peripheral drivers. As CPUs advanced in terms of clock speed and processing power, the I/O subsystem that supports the processor could not keep up. In fact, different links developed at different rates within the subsystem. The basic elements found on a motherboard include the CPU, Northbridge, Southbridge,PCI bus, and system memory. Other components are found on a motherboard, such as network controllers, USB ports, etc., but most generally communicate with the rest of the system through the Southbridge
4.HYPER TRANSPORT TECHNOLOGY SOLUTION
Hyper Transport technology, formerly codenamed Lightning Data Transfer (LDT), was developed at AMD with the help of industry partners to provide a high- speed, highperformance, point-to-point link for interconnecting integrated circuits on a board. With atop signaling rate of 1.6 GHz on each wire pair, a Hyper Transport technology link can support a peak aggregate bandwidth of 12.8 Gbytes/s.The Hyper Transport I/O link is a complementary technology for InfiniBand and1Gb/10Gb Ethernet solutions. Both InfiniBand and highspeed Ethernet interfaces are highperformance networking protocol and box-to-box solutions, while Hyper Transport is intended to support in-the-box connectivity. The Hyper Transport specification provides both link- and system-level power management capabilities optimized for processors and other system devices. The ACPI compliant power management scheme is primarily messagebased, reducing pin-count requirements. Hyper Transport technology is targeted at networking, telecommunications, compute rand high performance embedded applications and any other application in which high speed, low latency, and scalability is necessary. Hyper Transport technology addresses this bottleneck by providing a point-to point architecture that can support bandwidths of up to 51.2Gbps in each direction. Not all devices will require this much bandwidth, which is why Hyper Transport technology operates at many different frequencies and widths. Currently, the specification supports a frequency of up to 800MHz (sampled twice per period) and a width of up to 32-bits in each direction. Hyper Transport technology also implements fast switching mechanisms, so it provides low latency as well as high bandwidth. By providing up to 102.4Gbps aggregate bandwidth, Hyper Transport technology enables I/O-intensive applications touse the throughput they demand. In order to ease the implementation of Hyper Transport technology and provide stability, it was designed to be transparent to existing software and operating systems. Hyper Transport technology supports plug-and-play features and PCI-like enumeration, so existing software can interface with a Hyper Transport technology link the same way it does with current PCI buses. This interaction is designed to be reliable, because the same software will be used as before. In fact it may become more reliable, as data transfers will benefit from the error detection features Hyper Transport technology provides. Applications will benefit from Hyper Transport technology without needing extra support or updates from the developer. The physical implementation of Hyper Transport technology is straightforward, as it requires no glue logic or additional hardware. Hyper Transport technology specifications also stress a low pin count. This helps to minimize cost, as fewer parts are required to implement Hyper Transport technology, and reduces Electro-Magnetic Interference (EMI), a common problem in board layout design. Because Hyper Transport technology is designed to require no additional hardware, is ansparent to existing software, and simplifies EMI issues, it is a relatively inexpensive, easy-toimplement technology.
5.DESIGN GOALS
In developing Hyper Transport technology, the architects of the technology considered the design
goals presented in this section. They wanted to develop a new I/O
protocol for in-the-box I/O connectivity that would:
1. Improve system performance
- Provide increased I/O bandwidth
- Reduce data bottlenecks by moving slower devices out of critical information paths
- Ensure low latency responses
- Reduce power consumption
2. Simplify system design
- Reduce the number of buses within the system
- Use as few pins as possible to allow smaller packages and to reduce cost
3. Increase I/O flexibility
- Provide modular bridge
architecture
- Allow for differing upstream and downstream bandwidth requirements
4. Maintain compatibility with legacy systems
- Complement standard external buses
- Have little or no impact on existing operating systems and drivers
5. Ensure extensibility to new system network architecture (SNA) buses
6. Provide highly scalable multiprocessing systems
6.IMPLEMENTATION
Hyper Transport technology supports multiple connection topologies including daisy chain topologies, switch topologies and star topologies.
7.CONCLUSION
Hyper Transport technology is a new high-speed, high-performance, point-to-point link for integrated circuits. It provides a universal connection designed to reduce the number of buses within the system, provide a high-performance link for embedded applications, and enable highly scalable multiprocessing systems. It is designed to enable the chips inside of PCs and networking and communications devices to communicate with each other up to 48 times faster than with existing technologies. Hyper Transport technology provides an extremely fast connection that complements externally visible bus standards like the PCI, as well as emerging technologies like InfiniBand and Gigabit Ethernet. Hyper Transport technology is truly the universal solution for in-the-box connectivity.