18-09-2012, 12:24 PM
INTRODUCTION TO VERILOG HDL
VERILOG.ppt (Size: 286 KB / Downloads: 251)
What is verilog?
Verilog is a HDL- hardware description language to design the digital system.
VHDL is other hardware description language.
Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages
Verilog was introduced in 1985 by Gateway Design System Corporation
verilog
IEEE 1364-2001 is the latest Verilog HDL standard
Verilog is case sensitive (Keywords are in lowercase)
The Verilog is both a behavioral and a structure language
Elements of verilog- data type
Nets
Nets are physical connections between devices
Many types of nets, but all we care about is wire.
Declaring a net
wire [<range>] <net_name> ;
Range is specified as [MSb:LSb]. Default is one bit wide
Registers
Implicit storage-holds its value until a new value is assigned to it.
Register type is denoted by reg.
Declaring a register
reg [<range>] <reg_name>;
Parameters are not variables, they are constants.