12-06-2014, 10:40 AM
Implementation of 10T- SRAMs in 45-nm for Fast and Low power and comparing with other models
Implementation of 10T- SRAMs.pptx (Size: 364.1 KB / Downloads: 12)
Abstract
In this paper, we present a NATURE architecture that is based on CMOS logic and SRAMs that are used for on-chip dynamic reconfiguration.
Fast and low-power 10T SRAM blocks that are used in this design.
Verification with respect to 8T and 10T diff-pair SRAM cells
Implementation of 8T SRAM cell.
Verifing waveforms and Power dissipation
Implementation of 10T SRAM cell.
Verifing waveforms and Power dissipation