15-06-2012, 04:30 PM
Implementation of Reduced Power Open Core Protocol Compliant Memory System using VHDL
Implementation of Reduced Power Open Core Protocol.pdf (Size: 189.88 KB / Downloads: 43)
Introduction
Open Core Protocol is a signal exchange protocol over a family of on-chip core interfaces. OCP data transfer models range from simple request-grant handshaking through pipelined request-response to complex out-of order operations. The OCP defines a point-to-point interface between two communicating entities, such as IP cores and bus interface modules (bus wrappers) [1]. Given the wide range of IP core functionality, performance and interface requirements, a fixed definition interface protocol cannot address the full
Spectrum of system interface requirements. The need to support verification and test requirements adds an even higher level of complexity to the interface.
Open Core Protocol Compliant System
The availability of a common interface platform provided by OCP has inspired system designers to use them as replacements for other interface protocols.OCP compliance is obtained by creating a wrapper around the original designs to meet the OCP specification. A wrapper is a design which satisfies all the specifications given by the Open Core Protocol. Then the designs are interfaced. For Compliance the core must include at least one OCP interface. The core and OCP interfaces must be described using an RTL configuration file .Each OCP interface on the core must comply with all aspects of the OCP interface specification. There are three types of OCP Profiles (i) High Performance (HP) (ii) Generic Profile (GP) (iii) Peripheral Profile (PP) [2].
Memory Interface System
The scope of the research is that for understanding the OCP compliant system a model is needed since no such works exists in this field with experimental results. Hence a memory system with a Memory Controller as the OCP Master and Memory as OCP Slave is designed .First their performance is analyzed as the system itself is and then with the OCP wrapper.
The system includes an OCP compliant Memory Controller and a Memory where the memory controller acts as the OCP master and the Memory acts as the OCP Slave. This paper discusses the Peripheral OCP profile with Simple Write and Read transfer and Generic OCP profile with data handshaking and burst transfer [2].
Conclusions
A parameterizable and reconfigurable OCP compliant memory system specifically targeted to use with high speed applications is discussed here. The primary trigger to the development of such design is the lack of availability of a common interface that can be used with the different IP cores in a SoC design. This paper discusses the use of OCP for a memory system interface and concentrates on enhancing the memory system performance with different modes of Burst data transfer. Power Reduction with Multi voltage design is implemented with good results.