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Abstract—The fixed point processors are used only with
integers. To process real numbers, floating point processors are
required. Since these floating point processors are expensive, the
project aims at implementing the properties of floating point
processors into fixed point processors. This is achieved by proper
programing in high level languages like VHDL. The softwares
used for simulation are Xilinx ISE Design Suite 14.2 and
Modelsim 6.2C.
INTRODUCTION
Arithmetic circuits form an important class of circuits in
digital systems. With the remarkable progress in the area of
very large scale integration (VLSI) circuit technology, many
complex circuits, which were thought to be impossible have
become easily realisable today. Algorithms that were found to
be difficultto implement now have many implementation
possibilities for the future. It means that not only the
conventional computer arithmetic methods, but also the
unconventional ones are worth in new designs. Floating point
numbers can be used for representing both real and integer
numbers.The floating point numbers have wide applications as
it has greater dynamic range, high precision, better operation
rule and efficiency. The most common representation is that
defined by the IEEE 754 Standard. One of the most important
stages in fixed point to floating point conversion is the
evaluation of the floating point specification accuracy.
Floating point is a system for representing numbers that would
be too large or too small to be represented as integers. Floating
point representation is able to retain its resolution and
accuracy compared to fixed pointrepresentation. Numbers are
in generalrepresentedalmost approximately a fixed number of
significant digits and scaled using an exponent. The base for
the scaling is normally 2, 10 or 16. The typical number that
can be represented exactly is of the form: Significant digits
×Base exponent , S ×B[2]. In computing, floating point
explains a method of representing an approximation to real
numbers in a way that can support a wide range of values.
The IEEE has standardized the computer representation for
binary floating-point numbersin IEEE 754. It is the standard
followed by almost all modern machines. It is a difficult task
forthe computer manufacturers to decide a common
representation and arithmetic conventionfor floating point
data. The standard defines:
1.Arithmetic formats: sets of binary and decimal floating-point
data, which consist of finitenumbers (including signed zeros
and subnormal numbers), infinities, and special "not anumber"
values (NaNs)
2. Interchange formats: encodings (bit strings) that may be
used to exchange floating-pointdata in an efficient and
compact form.
3. Rounding rules: properties to be satisfied when rounding
numbers during arithmetic andconversions
4. Operations: arithmetic and other operations on arithmetic
formats
5. Exception handling: indications of exceptional conditions
(such as division by zero, overflow,etc.)
In recent years, Floating-point numbers are widely adopted in
many applications due toits high dynamic range and good
robustness against quantization errors. Floating
pointrepresentation is able to retain its resolution and
accuracy. IEEE specified standard forfloating-point
representation is known as IEEE 754 standard. The standard
specifies interchangeand arithmetic formats, methods for
binary and decimal floating-point arithmetic incomputer
programming areas. The main aim in implementing floating
point operation on reconfigurable hardware is to utilize less
chip area with less combinational delay which means greater
speed. A floating point adder and multiplier are implemented
using the VHDL language, using the Xilinx 14.2, SPARTAN
3E FPGA.
LITERATURE REVIEW
VHDL environment for floating point arithmetic and
logic unit design using pipelining is introduced; the novelty in
the ALU design. Pipelining provides a high performance
ALU. Pipelining is used to execute multiple instructions
simultaneously. In top-down design approach, four arithmetic
modules, addition, subtraction, multiplication and division are
combined to form a floating point ALU unit. Each module is
divided into sub- modules. The ALU design is realized using VHDL.The design functionalities are validated through VHDL
simulation. Synthesis and simulation results are found out in
the Xilinx12.1i platform.
The main objective is to explain the implementation of
pipelining in designing of floating point ALU using VHDL.
The other objectives are to design a 16-bit floating point ALU
operating on IEEE 754 standard. Floating point
representations support the four basic arithmetic operations:
addition, subtraction, multiplication and division. Second sub
objective is to study the behaviour of the ALU design using
VHDL.
Specifications for a 16-bit floating-point ALU design are as
follows:
1. Input A and B. The output result is a 16-bit binary floating
point.
2. Operands A and B operate as follows: A (operation)
B=results, operation can be addition (+), subtraction (-),
multiplication (*), division (/).
3. A 2-bit input signal selects ALU operation .
4. A 4-bit output signal which will work as a flag in
microprocessor.
5. Clock pulse is only applicable to the module which is
selected using demux.
6. Concurrent processes are used to allow the process to run in
parallel.
Design of IEEE - 754 Floating point Arithmetic processor
deals with the design of a 18-bit floating point arithmetic
processor for RISC/DSP processor applications. It is capable
of representing real and decimal numbers. The floating point
operations are inserted into the design as functions. The logic
for the mentioned is different from the ordinary arithmetic
functions. The numbers have to be first converted into the
standard IEEE floating point standard representation before
any kind of operations are conducted on them. The floating
point representation for a standard singleprecision number is a
18-bit number that is segmented to represent the floating point
number. The IEEE format consists of four fields, the sign of
the exponent, the next seven bits are that of the exponent
magnitude, and the remaining 10 bits represent the mantissa
sign. The exponent in this IEEEstandard is represented in
excess-127 format and all the arithmetic functions like
addition, subtraction, multiplication and division will be
designed by the processor.
The main functional blocks of floating point arithmetic
processor design includes, Arithmetic logic unit(ALU),
Register organization, control and decoding unit, memory
block, 18-bit floating point addition, subtraction,
multiplication and division . The processor IP core can be
embedded in many places such as coprocessor for DSP and
RISC controller. The overall system architecture will be
designed using HDL language and simulation, synthesis.
The simulation of performance of the proposed algorithm was
done in ModelSim using Verilog. A large sequence of bits was
generated randomly at the sender. The generated bits were
then divided into 64-bit blocks; each block was then encrypted
to a 128-bit block using M-DES. The encrypted blocks were
then assumed to be transmitted over the wireless channel. The encrypted blocks that contains error are then decrypted block
by block. Then, the resulted sequence of bits at the receiver
after decryption is compared with the sequence of bits at the
sender before encryption, and the error is calculated.
It showed how well known block encryption algorithms are
not sufficient for the use in wireless applications.The reason is
that in these applications, the signal may experience severe
degradations and attenuations, which causes wrong reception
of the signal and hence a drastic effect on the decryption
process. The paper,proposes a new encryption mechanism
based on modified DES. Using simulation , the performance
of the proposed M-DES versus the known standard DES and
Triple DES versus Triple M-DES can be calculated. It showed
that the new algorithm outperforms the standard DES and
Triple DES algorithms in terms of error performance. It also
showed that the new algorithm increased the security to a high
level which is prone to all applicable types of attacks.
A floating point arithmetic and logic unit using pipelining was
designed. By using pipeline with ALU design, ALU provides
a high performance. With pipelining and parallel processing
together, ALU execute multiple instructions simultaneously.
Floating point ALU unit is formed by combination of
arithmetic modules (addition, subtraction, multiplication,
division)and Universal gate module. Each module is divided
into sub-module. Bit selection determines which operation
takes place at a particular time.
18 bit floating point ALU is designed. Floating point
operations are hard to implement on Field Programmable Gate
Arrays (FPGA ) because of the complexity of algorithms.
Again, many scientific applications require floating point
arithmetic because requirement of high accuracy in their
calculations. In this paper an efficient implementation of an
IEEE 754 single precision floating point arithmetic unit is
designed in Xilinx SPARTAN 3E FPGA. VHDL environment
is required here for floating point arithmetic unit design using
pipelining, which provides high performance. Pipelining is
used to execute multiple instructions simultaneously.
In top-down design approach, four arithmetic modules,
addition, subtraction, multiplication and division are combined
to form a floating point arithmetic unit. FP addition is
implemented using Leading-One-Detector (LOD), LeadingOne-Predictor
(LOP) and two-path algorithms. In this ALU
for Adder module clock period is (LOD- 33.159ns, LOP-
28.358ns, Two-path- 22.313ns), for FP multiplier it is 10.402
ns, for FP divider it is 7.058ns. And the area in slices is for
Adder module it is (LOD- 694, LOP-731, Two- path- 1020),
for FP multiplier it is 272, for FP divider it is 185. Synthesis
and simulation results are obtained by using
Xilinx13.1i platform.
CONCLUSION
The properties of floating point ALU can be implemented in
fixed point architecture.It reduces the cost and size
requirements to a great extend. The VHDL language is used as
the programming tool. Xilinx 14.4 is used as the simulation
tool and it is implemented in the Spartan 3E FPGA.It has
higher accuracy.It is faster than fixed point operations.