05-09-2012, 03:10 PM
A Fully Differential CMOS Telescopic Operational Amplifier with Class AB Output Stage
1A Fully Differential.pdf (Size: 388.16 KB / Downloads: 104)
Abstract
The design of a fully differential CMOS transconductance operational amplifier is
presented. Topology selection, compensation, biasing, and common mode feedback are
discussed. Design analysis and simulations are presented demonstrating that the amplifier
exceeds the specifications for application in the first stage of a 13-bit pipelined A/D converter,
while dissipating an average of 66 mW of power.
INTRODUCTION
The operational amplifier is the workhorse of analog design. In this report, we present the design
of a fully differential transconductance amplifier to be used in the first stage in a pipelined 13-Bit
A/D converter. The design goal is to meet the specifications over all process corners, while
minimizing power.
This report is organized in the following manner. First, the considerations about topology are
presented. Second, the design process for the given topology is outlined. In addition, tradeoffs
and optimizations are explicitly discussed. Next, we present simulation results which verify that
our design meets the specifications over process corners. Finally, we conclude with a summary
discussion of our design.
TOPOLOGY CONSIDERATIONS
In choosing a topology, we first considered the high dynamic range requirement of the amplifier
which dictates that a relatively large compensation or loading cap be used to keep the total output
noise at a low level. Secondly, the fast settling time requirement implies that the amplifier must
be able to source large currents to charge this capacitor to avoid slew limitations. Thirdly, the
large DC gain requirement of 50,000, which is on the order of (gmro)3 to (gmro)4, indicates that at
least 3 gain devices be used in the signal path. This need to bias the amplifier at a relatively large
current, along with the need for a sizable output swing, makes it very difficult to meet the large
DC gain requirement (50,000) with only a single gain stage.
DESIGN OPTIMIZATION
As shown in our analysis, the design specifications can be met by keeping the VDSAT of
our devices close to 200mV. We made our initial design attempting to maintain this
VDSAT for our devices. Since we determined that flicker noise was negligible, we chose
our input devices to be NMOS devices to get the increased gm for a smaller gate
capacitance. We chose our first stage current to be 8mA based on the settling. This
mandates that the VDSAT of our input devices be less than 200mV to meet the gm
requirement for unity gain bandwidth thus we started with a VDSAT of 100mV for the
input devices. We biased our second stage transistors for a quiescent bias current of
10mA as a starting point to avoid the “non-linear slewing”. Initially, we sized all of our
transistors (except the input devices and M9), including the tail current source, to have a
VDSAT = 200mV with a channel length of 1um. M9 is sized for a VDSAT = 400mV so as to
bias M1 and M7 such that both are in saturation with some margin. The compensation
capacitor is set at 25pF while the external input and feedback capacitors are sized to get
F=1/4, which implies Cin = 2*Cg1.
DESIGN SUMMARY AND CONCLUSION
We have presented the design of a two-stage fully differential transconductance amplifier with a
telescopic input stage and a class AB output stage. It is compensated using cascode
compensation for greater bandwidth than with standard Miller compensation. The amplifier
meets all specifications over all process corners and dissipates less than 70mW of power.
By utilizing a design methodology rooted in solid theory, we believe that we have obtained a
near-optimal design. The power consumption of the biasing network, of course, could be greatly
reduced through device scaling.
For application in the highly demanding first stage of a cascoded 13-bit A/D converter, measures
must be taken to minimize the impact of device mismatch and amplifier offset. Device mismatch
can be reduced by appropriate layout techniques, and the offset can be cancelled by using the
appropriate switched capacitor circuit.