19-06-2012, 03:44 PM
MULTIPLIER IMPLEMENTATION FOR DSP PRCESSOR
MULTIPLIER IMPLEMENTATION FOR DSP PRCESSOR.pptx (Size: 724.72 KB / Downloads: 32)
Vhdl DEVELOPMENT
With the continuing developments of Vhdl technologies and tremendous shrinkage of process features, the need to develop process independent chip design tools are
growing.
The use of a hardware description language (HDL)for integrated circuit design eliminates the need to worry about process design rules at the early stages of design .
This reduces the design complexity and time required to complete chip designs.
This is very important since vendors need to market their products in the shortest possible time
TYPES OF MULTIPLIERs:
Outline
Survey Objectives
Basic Multiplication Schemes Shift/Add Multiplication Algorithm
High-Radix Multipliers
Tree and Array Multipliers Using carry/save adders
Full tree multipliers
Some of the types of multipliers that we discuss are Booth multipliers and Array multipliers.
Booth multiplier
Booth’s multiplication algorithm is extensively used in many computing machines.
This algorithm was invented by Andrew Booth in 1951. This algorithm is particularly useful for machines that can shift bits faster than adding them.
BOOTH MULTIPLIER
Booth multiplication is a technique that allows for smaller, faster multiplication circuits, by recoding the numbers that are multiplied.
It is possible to reduce the number of partial products by half, by using the technique of radix-4 Booth recoding .
The basic idea is that, instead of shifting and adding for every column of the multiplier term and multiplying by 1 or 0, we only take every second column, and multiply by ±1, ±2, or 0, to obtain the same results.
The advantage of this method is the halving of the number of partial products. To Booth recode the multiplier term, we consider the bits in blocks of three, such that each block overlaps the previous block by one bit.
Grouping starts from the LSB, and the first block only uses two bits of the multiplier. shows the grouping of bits from the multiplier term for use in modified booth encoding.
Array multiplier
A tree multiplier, with a one-sided reduction tree and a ripple-carry final adder is called an array multiplier
An array multiplier is very regular in its structure and uses only short wires that go from one FA to adjacent FA.
It has a very simple and efficient layout in VLSI and can be easily and efficiently pipelined