16-07-2012, 09:47 AM
OPTIMIZE THE PERFORMANCE OF MAC BASED ON RADIX-2 BOOTH ALGORITHM
OPTIMIZE THE PERFORMANCE OF MAC BASED ON RADIX-2 BOOTH ALGORITHM.pptx (Size: 602.37 KB / Downloads: 34)
Aim of the Project
To optimize the performance of multiplier and accumulator for Arithmetic-dominated circuits in DSP applications like audio signal processing, video/image processing and real time-signal processing.
Introduction
The MAC(Multiplier and Accumulator Unit) is used for image processing and digital signal processing (DSP) in a DSP processor.
The multiplier and multiplier-and-accumulator (MAC) are the essential elements of the digital signal processing such as filtering, convolution, and inner products.
The MAC on specific processor cannot be run at 100% efficiency.
Because they are basically accomplished by repetitive application of multiplication and addition, the speed of the multiplication and addition arithmetic determines the execution speed and performance of the entire calculation.
Due to the reasons of lower speed of MAC,
To improve speed of MAC on specific processor, MAC needs to be fast and hence must have a special algorithm for "multiplication" instruction.
Project Objectives
To decrease the delays by combining multiplication with accumulation.
Devising a hybrid type of carry save adder (CSA) in arithmetic operation (multipliers) to increase the performance.
Booth's Algorithm
Booth multiplication is a technique that allows for smaller, faster multiplication circuits, by recoding the numbers that are multiplied
Speed of arithmetic operations are dependent on the number of partial products and speed of accumulation of those partial products.
Methodology
The computations of multiplication and accumulation are combined and a hybrid-type CSA structure is proposed to reduce the critical path and improve the output rate.
In this, adders are replaced with compressor tree.
A carry look-ahead adder(CLA) is inserted in the CSA tree to reduce the number of bit in final adder
IMPLEMENTATION
Identify the Architecture From the literature survey
Model the Architecture into RTL [register transfer level]modeling
Verify the functionality of Modeled architecture in MODELSIM®
Synthesis the verified design in Xilinx ISE®
Generation of Bit map file for Dump into Spartan 3E FPGA
Program the Bit map file into FPGA.
Resources
Software and hardware resources to accomplish the project.
Software Resources
XILINX 9.2 ISE
MODELSIM SIMULATOR.
Hardware Resources
Spartan 3E FPGA
Conclusion
The overall MAC performance has been improved, by removing the independent accumulation process that has the largest delay and merging it to the compression process of the partial products and actual performance has been increased to about twice if the pipeline is incorporated