27-07-2012, 11:52 AM
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization
Reconfigurable ECO Cells.pdf (Size: 1.11 MB / Downloads: 29)
Abstract
Unused spare cells occur inevitably in traditional
engineering change order (ECO) design flow. It results in inefficient
area usage, more leakage, and more IR drop impacts. To
tackle these problems, a reconfigurable cell is proposed, which
serves the dual purposes of decoupling capacitance and spare cell
in this paper. Before ECO is applied, these cells are preplaced
as decoupling capacitors. When ECO is applied, these cells are
configured as functional cells. To demonstrate the efficiency of
our configurable cell, we propose an algorithm for timing closure
and IR drop minimization. Compared with traditional ECO flow,
our method shows 15% reduction in maximum IR drop and 9%
reduction in leakage before applying.
INTRODUCTION
SYNTHESIS and physical design methodologies from
leading suppliers have tremendously relied on engineering
change order (ECO) flow to solve timing closure issues and
accommodate incremental change of chip function. In conventional
ECO flow, redundant standard cells, known as spare
cells, are preplaced uniformly in CORE area for ECO changes.
Rather than building a new layout, ECO flow using spare
cells is employed so as to minimize impacts on original chip
layout. These spare cells are very effective in solving timing
closure [6], [7] and accommodating incremental change of chip
function [8], [10], however, at cost of extra area and leakage
overhead.
ECO USING NEW DESIGN STYLE
To demonstrate the effectiveness of our RECON ECO flow,
we will develop an algorithm to solve the timing closure
problem.
A. Problem Formulation
Before we formally define the problem, the following definitions
are presented.
1) An ECO path is a path that violates the timing constraint.
2) Gate sizing operation is a technique to change driving capability
of cell on the ECO path with partial reroute.
3) Buffer insertion operation is a technique to insert a buffer
along a path with partial reroute.
Now, our problem is defined as follows. Given a set of placed
gate-level netlist, ECO paths, and timing constraint, our objective
is to perform gate sizing or buffer insertion on ECO paths
so that timing constraint is met and IR drop is minimized.
EXPERIMENTS
Experiment Setup
Six benchmark examples with gates larger than 10 000 gates
are randomly selected from ITC99 benchmarks [4]. The benchmark
examples are first synthesized by Synopsys synthesis tool
to gate-level netlists in VERILOG format using 0.13 um standard
cells. Second, automatic placement-and-route tool by Cadence
[5] is applied to place standard cells and our RECON
cells. Then, IR drop and static timing analysis are performed.
Finally, given a set of ECO paths, RECON ECO Algorithm is
called. Fig. 9 illustrates our experimental flow. For comparison,
a traditional ECO flow is also performed, where spare cells including
inverter, two-input NAND, two-input NOR, and buffer
rather than RECON cells are preplaced. The same ECO algorithm
(Fig. 8) is applied, except that the candidate configurations
for timing improvement are spare cells at fixed location.