14-08-2012, 03:20 PM
Reversible Logic to Cryptographic Hardware: A New Paradigm
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INTRODUCTION
Side Channel attacks against cryptographic systems exploit
physical characteristics of a device, rather than direct codebreaking
methods. One such technique is Differential Power
Analysis (DPA), which uses the power consumption of a
cryptographic device such as a smartcard [1,2,3]. It is known
that the amount of power consumed by the device varies
depending on the data and the instructions performed during
different parts of an algorithm’s execution, thus an attacker
directly observes a device’s power consumption. By simply
examining power consumption traces, it is possible to determine
the characteristics of a cryptographic device and the key of the
cryptographic algorithm being used. In this work, we propose
the use of reversible logic to thwart attacks against
cryptographically secure hardware based on DPA. Researchers
have shown that for irreversible logic computations, each bit of
lost information generates kTln2 joules of heat energy, where k
is Boltzmann’s constant and T is the absolute temperature at
which the computation is performed [4]. Reversible circuits do
not lose information, and thus kTln2 joules of heat energy will
not be dissipated [5]. Furthermore, voltage-coded logic signals
have an energy of Esig = ½CV2, and this energy is dissipated
whenever the node voltage changes in the irreversible CMOS
technology. It is estimated that reversible logic also helps to
save energy by using charge recovery logic [7]. Younis has
fabricated an 8x8 reversible multiplier array using SCRL gates
and measured an energy saving of over 99% over conventional
CMOS implementations of the same circuits [8]. Thus, the
application of reversible logic to the field of hardware
cryptography is proposed here to guard against DPA attacks, as,
ideally, no energy will be dissipated in the reversible circuits.
Addition and modulo multiplication are the two major power
hungry operations in the ALU of a crypto-processor. Thus, this
paper proposes a reversible carry propagate adder, four-to-two
and five-to-two carry save adders (CSA) using a reversible TSG
gate [9,10,11,12]. Furthermore, a reversible Montgomery
multiplier [13] using the proposed reversible adders is shown.
The major requirement for a Montgomery multiplier is the
design of reversible sequential components, thus the authors
have also proposed the reversible sequential components like
latch, flip flop, register and shift register using the Fredkin gate.
The proposed reversible circuits form the primitive components
of the ALU of a reversible crypto-processor. As far as we know,
this is the first attempt to apply reversible logic to designing
secure cryptosystems.
REVERSIBLE TSG GATE
In order to implement the reversible designs of the carry
propagate, carry save adders and Montgomery multiplication, a
basic reversible TSG gate is discussed along with the term
‘garbage output’.
Proposed Reversible Sequential Circuits
Firstly, the reversible D latch is built from the Fredkin gate
which is later used to design complex sequential circuits, as
discussed in the section below. We have previously also
proposed designs of reversible sequential circuits. As far as we
can discover, this is the first work to design reversible
sequential circuits [20,21]. The proposed reversible sequential
designs are further modifications to the existing design
previously proposed. The Fredkin gate [22], is a (3*3)
conservative reversible gate originally introduced by Petri. It is
called a 3*3 gate because it has three inputs and three outputs.
The term conservative means that the Hamming weight
(number of logical ones) of its input equals the Hamming
weight of its output. The input triple (x1,x2,x3 ) generates the
output triple (y1, y2,y3) as follows:
CONCLUSION
This paper proposes the novel idea of applying reversible logic
for the design of secure cryptosystems. The reversible design of
carry propagate adder, five-to-two CSA and four-to-two CSA
adders has been demonstrated. Novel reversible sequential
circuits are also proposed. The proposed adder and sequential
units are used to design an efficient modular Montgomery
multiplier for use in hardware cryptosystems. The future work
in this direction is the comprehensive implementation of DES or
RSA using reversible logic, and to provide a rigorous analysis.
It is suggested that the proposed work will provide a new focus
in the cryptography field making hardware more secure against
DPA attacks and will also attract the attentions of computer
scientists towards applying reversible logic to hardware
cryptography.