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6868405-STATIC-TIMING-ANALYSIS.ppt (Size: 2.16 MB / Downloads: 398)
STATIC TIMING ANALYSIS
Introduction
Effective methodology for verifying the timing characteristics of a design without the use of test vectors
Conventional verification techniques are inadequate for complex designs
Simulation time using conventional simulators
Thousands of test vectors are required to test all timing paths using logic simulation
Increasing design complexity & smaller process technologies
Increases the number of iterations for STA
Simulation vs. Static timing
OVERVIEW
STA in ASIC Design Flow – Pre layout
STA in ASIC Design Flow – Post Layout
Basic terminologies
Pulse Width
Setup & Hold times
Signal slew
Clock latency
Clock Skew
Input arrival time
Output required time
Slack and Critical path
Recovery & Removal times
False paths
Multi-cycle paths
Pulse Width
Pulse width
It is the time between the active and inactive states of the same signa
Setup and Hold time
Setup time
For an edge triggered sequential element, the setup time is the time interval before the active clock edge during which the data should remain unchanged
Hold time
Time interval after the active clock edge during which the data should remain unchanged
Signal Slew
Signal (Clock/Data) slew
Amount of time it takes for a signal transition to occur
Accounts for uncertainty in Rise and fall times of the signal
Slew rate is measured in volts/sec
Clock Latency
Clock Latency
Difference between the reference (source) clock slew to the clock tree endpoint signal slew values
Rise latency and fall latency are specified
Clock Latency
Clock Skew
Clock Skew is a measure of the difference in latency between any two leaf pins in a clock tree.
between CLKA and CLKB
rise = 22-8 = 14
fall = 22-14 = 8
between CLKB and CLKC
rise = 8-7 = 1
fall = 14-4 = 10
between CLKA and CLKC
rise = 22-7 = 15
fall = 22-4 = 18
It is also defined as the difference in time that a single clock signal takes to reach two different registers
Input Arrival time
Input Arrival time
An arrival time defines the time interval during which a data signal can arrive at an input pin in relation to the nearest edge of the clock signal that triggers the data transition
Output required time
Output required time
Specifies the data required time on output ports.
Slack and Critical path
Slack
It is the difference between the required (constraint) time and the arrival time (inputs and delays).
Negative slack indicates that constraints have not been met, while positive slack indicates that constraints have been met.
Slack analysis is used to identify timing critical paths in a design by the static timing analysis tool
Critical path
Any logical path in the design that violates the timing constraints
Path with a negative slack
Slack Analysis – Data Path types
Slack analysis – data path types
Primary input-to-register paths
Delays off-chip + Combinational logic delays up to the first sequential device.
Register-to-primary output paths
Start at a sequential device
CLK-to-Q transition delay + the combinational logic delay + external delay requirements
Register-to-register paths
Delay and timing constraint (Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times.
Primary input-to-primary output paths
Delays off-chip + combinational logic delays + external delay requirements.
Hold Slack calculation
Actual data arrival time definition
Data Input Arrival Timemin + Data path delaymin
If the data path starts in a primary input,
Data Input arrivalmin = Input arrival timemin
If the data path starts at a register,
(Source Clock Edgemin + Source Clock Path Delaymin) = Data Input Arrivalmin
Required Stability time definition
(Destination Clock Edgemax + Destination Clock Path Delaymax) + Hold = Required Stability Timemax
Hold Slack definition
Actual Data Arrivalmin - Required Stability Timemax
Calculate the hold slack
Hold slack calculation
Setup Slack calculation
Actual data arrival time definition
Data Input Arrival Timemax + Data path delaymax
If the data path starts in a primary input,
Data Input arrivalmax = Input arrival timemax
If the data path starts at a register,
(Source Clock Edgemax + Source Clock Path Delaymax) = Data Input Arrivalmax
Required Stability time definition
(Destination Clock Edgemin + Destination Clock Path Delaymin) - Setup = Required Stability Timemin
Setup slack definition
Required Stability Timemin - Actual Data Arrivalmax
Calculate the setup slack
Setup slack calculation
Recovery and Removal time
Recovery time
Like setup time for asynchronous port (set, reset)
Removal time
Like hold time for asynchronous port (set, reset)
Recovery time
It is the time available between the asynchronous signal going inactive to the active clock edge
Removal time
It is the time between active clock edge and asynchronous signal going inactive
False Paths
False paths
Paths that physically exist in a design but are not logic/functional paths
These paths never get sensitized under any input conditions
Multi-cycle paths
Multi-cycle paths
Data Paths that require more than one clock period for execution
Sequential Circuit Timing
Objectives
This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives:
Define the following global timing parameters and show how they can be derived from the basic timing parameters of flip-flops and gates.
Maximum Clock Frequency
Maximum allowable clock skew
Global Setup and Hold Times
Discuss ways to control the loading of data into registers and show why gating the clock signal to do this is a poor design practice.
Maximum Clock Frequency
The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flip-flops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency.
Relevant timing parameters
Gates:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
Flip-Flops:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
Setup time: tsu
Hold time: th
Example
Example
Example
Example
If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be skewed between these flip-flops. The difference between the times of arrival at the flip-flops is said to be the amount of clock skew.
Clock skew is due to different delays on different paths from the clock generator to the various flip-flops.
Different length wires (wires have delay)
Gates (buffers) on the paths
Flip-Flops that clock on different edges (need to invert clock for some flip-flops)
Gating the clock to control loading of registers (a very bad idea)
Example (Effect of clock skew on clock rate)
Clock C2 skewed after C1
Clock C1 skewed after C2
Summary of maximum clock frequency calculations
Maximum Allowable Clock Skew
How much skew between C1 and C2 can be tolerated in the following circuit?
Case 1: C2 delayed after C1
Case 2: C1 delayed from C2
How does additional delay between the flip-flops affect the skew calculations?
Summary of allowable clock skew calculations
Example: What is the minimum clock period for the following circuit under the assumption that the clock C2 is skewed after C1 (i.e., C2 is delayed from C1)?
First calculate the maximum allowable clock skew.
Next calculate the minimum clock period due to the path from Q1 to D2.
Finally calculate the minimum clock period due to the path from Q2 to D1
Global Setup Time, Hold Time and Propagation Delay
Global setup and hold times (data delayed)
Global setup & hold time (clock delayed)
Global setup & hold time (data & clock delayed)
Global propagation delay
Summary of global timing parameters
Example
Find TSU and TH for input signal LD relative to CLK.
Register load control (gating the clock)
A very bad way to add a load control signal LD to a register that does not have one is shown below
The reason this is such a bad idea is illustrated by the following timing diagram.
The flip-flop sees two rising edges and will trigger twice. The only one we want is the second one.
If LD was constrained to only change when the clock was low, then the only problem would be the clock skew.
If gating the clock is the only way to control the loading of registers, then use the following approach:
There is still clock skew, but at least we only have one triggering edge.
The best way to add a LD control signal is as follows: