05-10-2016, 10:14 AM
Sleep Transistor Design and Implementation – Simple Concepts Yet Challenges
To Be Optimum
1457779294-sleeptransistorsizing.pdf (Size: 94.01 KB / Downloads: 9)
ABSTRACT
Optimum sleep transistor design and implementation are critical
to a successful power-gating design. This paper describes a number
of critical considerations for the sleep transistor design and
implementation including header or footer switch selection, sleep
transistor distribution choices and sleep transistor gate length, width
and body bias optimization for area, leakage and efficiency.
INTRODUCTION
Leakage power has been increasing exponentially with the
technology scaling [1][2]. In 90nm node, leakage power can be as
much as 35% of chip power. Consequently, leakage power reduction
becomes critical in low-power applications such as cell phone and
handheld terminals. Power-gating is the most effective standbyleakage
reduction method recently developed [3]-[6]. In the power
gating, sleep transistors are used as switches to shut off power
supplies to parts of a design in standby mode. Although the concept
of the sleep transistor is simple, design of a correct and optimal sleep
transistor is challenge because of many effects introduced by the
sleep transistor on design performance, area, routability, overall
power dissipation, and signal/power integrity. Currently, many of the
effects have not been fully aware by designers. This could result in
improper sleeper transistor design that would either fail to meet
power reduction target when silicon is back or cause chip
malfunction due to serious power integrity problems introduced. We
have carried out comprehensive investigations on various effects of
sleep transistor design and implementations on chip performance,
power, area and reliability. In this paper, we shall describe a number
of critical considerations in the sleep transistor design and
implementation including header or footer switch selection, sleep
transistor distribution choices and sleep transistor gate length, width
and body bias optimization for area, leakage and efficiency.
A sleep transistor is referred to either a PMOS or NMOS high
Vth transistor that connects permanent power supply to circuit power
supply which is commonly called “virtual power supply”. The sleep
transistor is controlled by a power management unit to switch on and
off power supply to the circuit. The PMOS sleep transistor is used to
switch VDD supply and hence is named “header switch”. The
NMOS sleep transistor controls VSS supply and hence is called
“footer switch”. In sub-90nm designs, either header or footer switch
is only used due to the constraint of sub-1V power supply voltage.
FINE-GRAIN VS. COARSE-GRAIN SLEEP
TRANSISTOR IMPLEMENTATIONS
The sleep transistors can be implemented in a design in either
“coarse-grain” or “fine-grain” power gating styles. In the “finegrain”
implementation, the sleep transistor is inserted in every
standard cell which is often called MTCMOS cell. A power gating control signal is added to switch on and off power supply to the cell.
A weak pull-up/down transistor controlled by the sleep signal is
added to prevent floating output when the cell is in sleep mode. This
is necessary to prevent short circuit current in those active cells
connected to the sleep cell due to floating inputs. The pull-up/down
transistor remains in OFF state in normal operation mode. Only one
isolation state is allow which is “1” in footer switch implementations
and “0” in the header switch implementations.
The advantage of the fine-grain sleep transistor
implementations is that the virtual power nets (VVSS or VVDD) are
short and hidden in the cell. Moreover, the MTCMOS cell can be
implemented by existing standard cell based synthesis and
place&route tools. However, the fine-grain sleep transistor
implementation adds a sleep transistor to every MTCMOS cell that
results in significant area increase. Also, it is not able to use the
normal standard cells provided by library vendors and ASIC
foundries. Another issue is that the MTCMOS cells become more
sensitive to PVT variations, because the built-in sleep transistor is
subject to PVT variation which results in added IR-drop variation in
the cell and hence performance variation.
In the “coarse-grain” power gating designs as shown in Fig. 2,
the sleep transistors are connected together between the permanent
power supply and the virtual power supply networks.
HEADER VS. FOOTER SWITCH
The header switch is implemented by PMOS transistors to control
Vdd supply. PMOS transistor is less leaky than NMOS transistor of a
same size. The NBTI effect increases Vth over time and makes
PMOS transistor even less leaky. Header switches turn off VDD and
keep VSS on. As the result, it allows a simple design of a pull-down
transistor to isolate power-off cells and clamp output signals in “0”
state as shown in Fig.1. The “0” state isolation is complied with
reset state requirement in most designs. The disadvantage of the
header switch is that PMOS has lower drive current than NMOS of a
same size, though difference is reduced by strained silicon
technology. As a result, a header switch implementation usually
consumes more area than a footer switch implementation.
The footer switch is implemented by NMOS transistor to control
VSS supply. The advantage of footer switch is the high drive and
hence smaller area. However, NMOS is leakier than PMOS and
application designs become more sensitive to ground noise on the
virtual ground (VVSS) coupled through the footer switch. The
isolation on “0” state becomes complex due to loss of the virtual
ground in sleep mode and necessity of bypassing footer switch to
reach permanent VSS. In the following part of the paper, we shall
focus on header switch design and implementations.
GRID VS. RING STYLE SLEEP TRANSISTOR
IMPLEMENTATION
The sleep transistor has limited drive and relative high impedance
compared with metal power rails. Consequently, sleep transistors are
usually implemented as an array to provide sufficient drive current in
a power gating design. The array can be implemented either in a ring
style or a grid distribution.
SLEEP TRANSISTOR DESIGN CONSIDERATIONS
The sleep transistor implementation introduces extra cost in chip
area, routing resource, IR-drop and design complexity. There are also
extra power dissipations from sleep transistors, power-gating control
logic and power-on/off introduced operations. It is essential to ensure
that the leakage reduction from the power gating implementation
overwhelms those introduced costs to be worth the effort. To that
end, various design considerations and tradeoffs need to be analyzed
and handled correctly in the sleep transistor design and
implementations. A good sleep transistor design is achieved by
optimizing gate length and width, finger size and body-bias based on
overall considerations of power efficiency, leakage current, IR-drop,
area efficiency and layout impact.
SLEEP TRANSISTOR EFFICIENCY (Ion/Ioff)
The sleep transistor efficiency is defined by a ratio of drain
current in ON and OFF states, i.e. Ion/Ioff. It is desirable to
maximize the efficiency to achieve high drive in normal operation
and low leakage in sleep mode. The sleep transistor efficiency can be
analyzed by SPICE simulations where two high Vth transistors are
configured for ON and OFF state respectively to measure Ion and
Ioff. A high temperature is set on ON sleep transistor to model high
chip temperature in operating mode and a low temperature is set on
OFF sleep transistor to reflect the cool situation when the design is in
sleep mode. The sleep transistor efficiency varies with gate length,
width and body bias as shown by the curves in Fig. 5. The curves
were generated by SPICE simulation of a TSMC90G high Vth
PMOS transistor with foundry provided BSIM4 v2.0 model. The
junction temperature of the transistor is set 125Co
in Ion analysis and
25Co
in Ioff analysis. Vds is set equal to Vdd in Ioff analysis and
10mV in Ion analysis reflecting the IR-drop target on the sleep
transistor.
The sleep transistor efficiency increases with gate length (Lgate)
and reaches peak at 130nm, mainly due to consequent Vth increase
with Lgate and hence sub-threshold leakage current reduction.
However, the efficiency declines after 130nm Lgate where Ion
reduction with Lgate becomes more significant than leakage
reduction. The efficiency also depends on gate width (Wgate). It
drops quickly with increase of Wgate until Wgate reaches 1.6um.
After that, it is level with Wgate. From efficiency point of view, a
combination of long gate length at 130nm and small gate width is
apparently a good choice.
The sleep transistor efficiency also depends on body bias because
reversed body bias increases Vth and hence smaller sub-threshold
leakage and higher efficiency. To evaluate the effect of body bias on
the sleep transistor efficiency, we repeated the analysis above with
various body biases
IR-DROP CONSIDERATIONS
Besides Ion/Ioff efficiency, leakage current and drive current, IRdrop
on sleep transistors must be considered in sleep transistor
optimization in terms of gate length, width and body bias. IR-drop on
the sleep transistor is tightly linked with equivalent channel
resistance (Ron = Vds/Ids) when the sleep transistor is conducting.
The smaller Ron, the smaller IR-drop. In a sub-50mV Vds region,
Ron is linearly increased with gate length and body bias as shown by
solid curves in Fig. 8. Ron is more sensitive to Lgate than Vbb.
From the Ron and leakage curves in Fig. 8, we can see that at a same
leakage current of 0.5nA (red and black dash lines), Ron is 1K Ohm
(red solid line) in the sleep transistor of 100nm Lgate and 1.6V body
bias compared with 1.5K Ohm (black solid line) in the sleep
transistor of 180nm Lgate and normal (1V) body bias. It is clear the
applying reversed body bias is a better choice than increasing gate
length for Ron and leakage current reduction.
CONCLUSION
Although the concept of sleep transistor is simple, optimum sleep
transistor design and implementation require optimizing all together
the gate length, width and body bias with overall considerations of
efficiency, leakage, drive, area and IR-drop effects which are often
conflicting and need to be weighted based on application
requirements. Increasing Lgate results in higher Vth and hence
lower leakage and higher Ion/Ioff efficiency, at price of significant
increase of Ron and decrease of Ion. Applying optimal reversed body
bias is more efficient and effective alternative to produce a higher
efficiency and Ion and lower Ron and Ioff sleep transistor than by
increasing Lgate. Correct choices in sleep transistor implementations
such as header or footer switch and ring or grid distributions are also
important.