30-11-2012, 06:30 PM
FPGA Implementation of parallel system for three (15, k) Binary BCH Encoders Using VHDL
FPGA Implementation.pptx (Size: 890.94 KB / Downloads: 51)
ABSTRACT-
1. Design three (15,k) BCH Encoders using VHDL
Implementation of (15,k) BCH Encoder on Xilinx Spartan3 FPGA
3. Simulation & synthesis using Xilinx ISE 10.1
4. Design & Implemention of the Parallel system
OBECTIVE
Design single bit error-correcring BCH code (15,11,1)
Design double bit error-correcting BCH code (15,7,2)
Design three bit error-correcting BCH code (15,5,3)
Design parallel system
Design of Encoder for (15, 11, 1) BCH Code
Design Encoder for (15, 11, 1) single error correcting BCH code by organizing LFSR
with generated polynomial 1+x+x4 Implement on Spartan 3 S1000 FPGA of Xilinx.
RTL view & Schematic by synthesis with Xilinx ISE 10.1, shown in Fig 3 and Fig. 4
CONCLUSION
Next stage of (15,k) BCH encoder is not possible so we use parallel system for (15,11,1) ,(15,7,2) & (15,5,3) for correcting data at receiver side according to requirement. The speed and device utilization can be improved by adopting parallel approach methods.