05-09-2012, 03:27 PM
Hi,
I am a student of Elec. & Electronics Eng.
I have an assignment to write VHDL program for a BCD-Decimal Decoder.
I have written the program code but I am having trouble with writing a test bench for my code. My code is listed as follows:
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library ieee;
use ieee.std_logic_1164.all;
entity bcdtod1_ckt is
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
y0 : out std_logic;
y1 : out std_logic;
y2 : out std_logic;
y3 : out std_logic;
y4 : out std_logic;
y5 : out std_logic;
y6 : out std_logic;
y7 : out std_logic;
y8 : out std_logic;
y9 : out std_logic);
end bcdtod1_ckt;
architecture bcdtod1_ckt_ar of bcdtod1_ckt is
signal a0, a1, a2, a3, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9: std_logic;
begin -- bcdtod1_ckt_ar
y0 <= (not a0)and(not a1)and(not a2)and(not a3);
y1 <= a0 and(not a1)and(not a2)and(not a3);
y2 <= (not a0)and a1 and(not a2)and(not a3);
y3 <= a0 and a1 and (not a2)and(not a3);
y4 <= (not a0)and(not a1)and a2 and (not a3);
y5 <= a0 and (not a1)and a2 and(not a3);
y6 <= (not a0)and a1 and a2 and (not a3);
y7 <= a0 and a1 and a2 and (not a3);
y8 <= (not a0)and(not a1)and(not a2)and a3;
y9 <= a0 and (not a1)and(not a2)and a3;
end bcdtod1_ckt_ar;
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