19-07-2012, 09:46 AM
VHDL Coding Basics
2code_basic.ppt (Size: 1.16 MB / Downloads: 78)
Entity
Define inputs and outputs
Example:
Entity test is
Port( A,B,C,D: in std_logic;
E: out std_logic);
End test;
VHDL features
Case insensitive
inputa, INPUTA and InputA are refer to same variable
Comments
‘--’ until end of line
If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line
Statements are terminated by ‘;’
Signal assignment:
‘<=’
User defined names:
letters, numbers, underscores (‘_’)
start with a letter
VHDL structure
Library
Definitions, constants
Entity
Interface
Architecture
Implementation, function
VHDL - Library
Include library
library IEEE;
Define the library package used
use IEEE.STD_LOGIC_1164.all;
Define the library file used
For example, STD_LOGIC_1164 defines ‘1’ as logic high and ‘0’ as logic low
output <= ‘1’; --Assign logic high to output
VHDL - Entity
It is the interface for communication among different modules / components and define the signal port modes (INPUT and OUTPUT)
VHDL - Entity
Input port can only be read inside architecture
input1 <= temp; -- This statement is NOT allowed
Output port can only be written inside architecture
temp <= output1; -- This statement is NOT allowed
Design using VHDL
Define the logic function
output <= inputa and inputb;
output is assigned to be inputa AND inputb
LHS contains only 1 variable only
RHS can be logics operations for many variables
Final code
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TEST IS
PORT (A,B,C,D : IN STD_LOGIC;
E : OUT STD_LOGIC);
END TEST;
ARCHITECTURE BEHAVIOR OF TEST IS
SIGNAL X,Y : STD_LOGIC;
BEGIN
X <= (not A) AND B;
Y <= C AND D;
E <= X OR Y;
END BEHAVIOR;
Final code
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TEST IS
PORT (A,B,C,D : IN STD_LOGIC;
E : OUT STD_LOGIC);
END TEST;
ARCHITECTURE BEHAVIOR OF TEST IS
SIGNAL X,Y : STD_LOGIC;
COMPONENT Chip_A
PORT (L,M,N : IN STD_LOGIC;
O,P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT Chip_B
PORT (Q,R,S : IN STD_LOGIC;
T : OUT STD_LOGIC);
END COMPONENT;
BEGIN
Chip1 : Chip_A
PORT MAP (A,B,C,X,Y);
Chip2 : Chip_B
PORT MAP (X,Y,D,E);
END BEHAVIOR;
Process
All statements in a process occur sequentially
If statements are defined in a process statement
Processes have sensitivity list
Process (A,B,C)
Begin
instructions
End process;