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VHDL
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INTRODUCTION
OVERVIEW
VHDL is an acronym which stands for VHSIC Hardware Description Language. VHSIC is another acronym which stands for Very High Speed Integrated Circuits. Hardware description languages can be used in several ways; they can be an alternative way of representing a circuit diagram for a digital circuit or a higher level algorithmic ‘program’ that solves a particular problem. Such structural or behavioural representations are two ways of describing a model of a digital system. VHDL can be used for documentation, verification, and synthesis of large digital designs. This is actually one of the key features of VHDL, since the same VHDL code can achieve all three of these goals, thus saving a lot of effort and reducing the introduction of errors between translating a specification into an implementation. In addition to being used for each of these purposes, VHDL can be used to take three different approaches to describing hardware. These three different approaches are the structural, data flow, and behavioural methods of hardware description. Most of the times a mixture of the three methods are employed and complete design will have different sections expressed in different ways. The terms algorithmic and RTL (Register Transfer Language) are sometimes used for behavioural and dataflow. A language capable of such diverse applications has a lot of keywords and atypical user only uses a small subset of the full language. It also means that there is often more than one way of doing something in VHDL; proper software tools that compile and run (i.e. simulate) the VHDL model will work with the entire languages defined in the official Language Reference Manual (LRM) but there will become specialist tools that require certain subsets or a particular methodology to be adhered to. This is most often seen in synthesis tools that try to automate the conversion of behavioural to structural. Implementation tools that are targeted to a particular type of hardware such as PLDs may well have restrictions and some of the less expensive VHDL tools may not completely cover the language. The Alliance toolset for instance is a free VHDL compiler, simulator and synthesis tool that runs on PCs; it has several restrictions. In practice such tools will still allow useful work to be done, within their target environment so the restrictions are rarely too severe. VHDL is a standard (VHDL-1076) developed by the IEEE. The language has been through a couple of revisions, the most widely used version is the 1987 (Stud 1076-1987) version, sometimes referred to as VHDL’87, but also just VHDL. However, there is a newer revision of the language referred to as VHDL’93. VHDL’93(adopted in 1994 of course) is fairly new and is still in the process of replacingVHDL’87. The appendix at the end of this document lists further reading for these standards and the library has some videotapes that describe the differences; they are unlikely to be of concern to the neophyte VHDL programmer/designer.
STANDARDIZATION
The standardization process for VHDL was unique in that the participation and feedback from industry was sought at an early stage. A baseline language (version7.2) was published 2 years before the standard so that tool development could begin in earnest in advance of the standard. All rights to the language definition were given away by the Dodd to the IEEE in order to encourage industry acceptance and investment.
1.2.3 ASIC MANDATE
Dodd Mil Stud 454 mandates the supply of a comprehensive VHDL description with every ASIC delivered to the Dodd. The best way to provide the required level of description is to use VHDL throughout the design process.
VHPI
In 2007, an amendment to VHDL 2002 was created. This introduces the VHDL Procedural Interface (VHPI) and also makes a few minor changes to the text of VHDL 2002. Apart from the VHPI itself, no new features were added to VHDL. The VHPI allows tools programmable access to a VHDL model before and during simulation. In other words, you can write programs in a language such as C that interact with a VHDL simulator.
1.2.7 VHDL-2008
Since the publication of the first IEEE standard in 1987 several revised version shave appeared. The first, in 1993, had the most extensive changes. VHDL 2000Edition introduced protected types and VHDL-2002 contains mainly minor changes. VHDL-2008 is the name of the new version of VHDL. As with the earlier revisions, this doesn’t radically alter the language, but it does provide a wider setoff modification than previously. A draft of the proposed revision (version 4.0) was delivered by Accelerate to thieve in 2008. The standard is now available from the IEEE and is known as Yeast. [1976-2008]
VHDL APPLICATION FIELD
VHDL is used mainly for the development of Application Specific Integrated Circuits (ASICs). Tools for the automatic transformation of VHDL code into a gate-level net list were developed already at an early point of time. This transformation is called synthesis and is an integral part of current design flows. For the use with Field Programmable Gate Arrays (FPGAs) several problems exist. In the first step, 7ehavio equations are derived from the VHDL description, no matter, whether an ASIC or a FPGA is the target technology. But now, this7ehavio code has to be partitioned into the configurable logic blocks (CLB) of the FPGA. This is more difficult than the mapping onto an ASIC library. Another big problem is the routing of the CLBs as the available resources for interconnections are the bottleneck of current FPGAs. While synthesis tools cope pretty well with complex designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used for the design of low complexity Programmable Logic Devices (PLDs).VHDL can be applied to model system 7ehavior independently from the target technology. This is either useful to provide standard solutions, e.g. for microcontrollers, error correction (de-)coders, etc., or behavioural models of microprocessors and RAM devices are used to simulate a new device in its target environment. An on-going field of research is the hardware/software co-design. The most interesting question is which part of the system should be implemented in software and which part in hardware. The decisive constraints are the costs and the resulting performance.
1.4 ASIC DEVELOPMENT
The development of VHDL models starts with their specification which covers functional aspects and the timing behaviour. Sometimes a behavioural VHDL models derived from there, yet synthesizable code is frequently requested right from the beginning. VHDL code can be simulated and checked for the proper functionality. If the model shows the desired behaviour, the VHDL description will be synthesized. A synthesis tool selects the appropriate gates and flip-flops from the specified ASIC library in order to reproduce the functional description. It is essential for the synthesis procedure that the sum of the resulting gate delays along the longest paths (from the output to the input of every Flip Flop) is less than the clock period. As soon as a model built of ASIC library elements is available, a simulation on gate level can be performed. Now gate and propagation delays have to be taken into account. Delay values can be included in each VHDL model description, i.e. The designer receives the first clues about maximum clock frequency and critical paths after synthesis, already. The propagation delay along the signal wires have to be estimated first because the real values are available after the layout is finished. The process of feeding these values back into the VHDL model is called back annotation. Once again it must be checked, whether the circuit fulfils the specified timing constraints.
The architecture had a mesh of horizontal and vertical interconnect tracks. At each junction was a fuse. With the aid of software tools, designers could select which junctions would not be connected by “blowing” all unwanted fuses. (This was done by a device programmer, but more commonly these days is achieved with ISP).Input pins were connected to the vertical interconnects. The horizontal tracks were connected to AND-OR gates, also called “product terms”. These in turn connected to dedicated flip-flops, whose outputs were connected to output pins. PLDs provided as much as 50 times more gates in a single package than discrete logic devices! This was a huge improvement, not to mention fewer devices needed in inventory and a higher reliability over standard logic. PLD technology has moved on from the early days with companies such as Xilinx producing ultra-low- power CMOS devices based on flash memory technology.
3 BASIC DESIGN FLOW
Design entry or design specification can be in the form of schematic capture or hardware description language (HDL). In schematic form, after determining the capture tool and the manufacturer’s library, designer can connect the gates from library with wires and then generates net list, which is the textual description of the circuit. Schematic capture is not feasible for large designs because it is not scalable, not reusable, strongly vendor dependent and hard to maintain. In HDL design entry, the design is entered in high level description language emphasizing design’s function or behaviour and then synthesized by the vendor independent tool and net list is generated. The design is more maintainable, scalable and reusable than schematic design entry. In design implementation, the first step is translation of low level and generic net list file into device specific resources. After translation step, mapping step checks the design according to device specific rules, add further logic or make replications to meet the timing requirements using device resources. At last, in place and route step, already allocated resources are distributed along FPGA taking into account the physical constraints and routing resources. At this point physical layout is determined and timing information for design entities and interconnects (Back Annotation) is available. After routing, the device is ready to be programmed. In device programming stage, the SRAM based FPGA’s configuration, which is volatile after power on and also defining the logic and interconnect, is programmed to a Programmable Read Only Memory (PROM) device with part name xc18v02. Design specification is a parallel process to design development. Design entry in either schematic or HDL form can be simulated behaviourally, while it can be tested based on the code syntax. After synthesis phase, generated net list format can be simulated functionally by providing test vectors and tested by checking the desired output vector. Timing simulation comes after the place and route phase by using back annotation.
1 CONCLUSION
The VHDL is a versatile language, which has great flexibility of designing components. It can be said that VHDL fuelled modern synthesis technology and enabled the development of ASIC semiconductor companies. From the beginningVHDL has been a powerful language with numerous language constructs that are capable of describing very complex behaviour, this leadership of VHDL community has assured open and internationally accredited for the electronic designEngineering community. The legacy of team work continues to benefit the designcommunity today as the benchmark by which one measures openness. With the help of which we are able to successfully implement the Arithmetic Logic Unit of a Microprocessor.