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VHDL is a hardware description language for modeling digital circuits that can range from the simple
connection of gates to complex systems. VHDL is an acronym for VHSIC Hardware Description Language, and
VHSIC in turn is an acronym for Very High Speed Integrated Circuits. This appendix gives a brief summary of the
basic VHDL elements and its syntax. Many advanced features of the language are omitted. Interested readers should
refer to other references for detailed coverage.
D.1 Basic Language Elements
D.1.1 Comments
Comments are preceded by two consecutive hyphens ( -- ) and are terminated at the end of the line.
Example:
-- This is a comment
D.1.2 Identifiers
VHDL identifier syntax:
• A sequence of one or more uppercase letters, lowercase letters, digits, and the underscore
• Upper and lowercase letters are treated the same (i.e., case insensitive)
• The first character must be a letter
• The last character cannot be the underscore
• Two underscores cannot be together
D.1.3 Data Objects
There are three kinds of data objects: signals, variables, and constants.
•
•
•
The data object SIGNAL represents logic signals on a wire in the circuit. A signal does not have memory;
thus, if the source of the signal is removed, the signal will not have a value.
A VARIABLE object remembers its content and is used for computations in a behavioral model.
A CONSTANT object must be initialized with a value when declared, and this value cannot be changed.
Example:
SIGNAL x: BIT;
VARIABLE y: INTEGER;
CONSTANT one: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
D.1.4 Data Types
BIT and BIT_VECTOR
The BIT and BIT_VECTOR types are predefined in VHDL. Objects of these types can have
BIT_VECTOR type is simply a vector of type BIT. A vector with all bits having the same value
the OTHERS keyword.
Example:
the values 0 or 1. The
can be obtained using
Digital Logic and Microprocessor Design with VHDL
Copyright Enoch Hwang
Appendix D− VHDL Summary
Page 3 of 23
SIGNAL x: BIT;
SIGNAL y: BIT_VECTOR(7 DOWNTO 0);
x <= '1';
y <= "00000010";
y <= (OTHERS => '0'); -- same as "00000000"
STD_LOGIC and STD_LOGIC_VECTOR
The STD_LOGIC and STD_LOGIC_VECTOR types provide more values than the BIT type for modeling a real circuit
more accurately. Objects of these types can have the following values.
'0'
'1'
'Z'
'−'
'L'
'H'
'U'
'X'
'W'
− normal 0
− normal 1
− high impedance1
− don’t-care2
− weak 02
− weak 12
− uninitialized2
− unknown1
− weak unknown2
The STD_LOGIC and STD_LOGIC_VECTOR types are not predefined, and so the following two library statements
must be included in order to use these types.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
If objects of type STD_LOGIC_VECTOR are to be used as binary numbers in arithmetic manipulations, then either
one of the following two USE statements must also be included
USE IEEE.STD_LOGIC_SIGNED.ALL;
for signed number arithmetic, or
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
for unsigned number arithmetic. A vector with all bits having the same value can be obtained using the
keyword, as shown in the next example.
Example:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
SIGNAL x: STD_LOGIC;
SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);
x <= 'Z';
y <= "0000001Z";
y <= (OTHERS => '0'); -- same as "00000000"
OTHERS
1
2
Must use uppercase. This is only a MAX+plus II restriction.
MAX+plus II only supports the values 0, 1, Z, and X.
Digital Logic and Microprocessor Design with VHDL