05-11-2012, 04:40 PM
VHDL Tutorial
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Introduction
The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes
facilities for describing logical structure and function of digital systems at a
number of levels of abstraction, from system level down to the gate level. It is intended,
among other things, as a modeling language for specification and simulation. We
can also use it for hardware synthesis if we restrict ourselves to a subset that can be
automatically translated into hardware.
VHDL arose out of the United States government’s Very High Speed Integrated
Circuits (VHSIC) program. In the course of this program, it became clear that there
was a need for a standard language for describing the structure and function of integrated
circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was
developed. It was subsequently developed further under the auspices of the Institute
of Electrical and Electronic Engineers (IEEE) and adopted in the form of the IEEE Standard
1076, Standard VHDL Language Reference Manual, in 1987. This first standard
version of the language is often referred to as VHDL-87.
Like all IEEE standards, the VHDL standard is subject to review at least every five
years. Comments and suggestions from users of the 1987 standard were analyzed by
the IEEE working group responsible for VHDL, and in 1992 a revised version of the
standard was proposed. This was eventually adopted in 1993, giving us VHDL-93. A
further round of revision of the standard was started in 1998. That process was completed
in 2001, giving us the current version of the language, VHDL-2002.
This tutorial describes language features that are common to all versions of the
language. They are expressed using the syntax of VHDL-93 and subsequent versions.
There are some aspects of syntax that are incompatible with the original VHDL-87 version.
However, most tools now support at least VHDL-93, so syntactic differences
should not cause problems.
The tutorial does not comprehensively cover the language. Instead, it introduces
the basic language features that are needed to get started in modeling relatively simple
digital systems. For a full coverage, the reader is referred to The Designer’s Guide to
VHDL, 2nd Edition, by Peter J. Ashenden, published by Morgan Kaufman Publishers
(ISBN 1-55860-674-2).
Modeling Digital Systems
The term digital systems encompasses a range of systems from low-level components
to complete system-on-a-chip and board-level designs. If we are to encompass this
range of views of digital systems, we must recognize the complexity with which we
are dealing. It is not humanly possible to comprehend such complex systems in their
entirety. We need to find methods of dealing with the complexity, so that we can,
with some degree of confidence, design components and systems that meet their requirements.
The most important way of meeting this challenge is to adopt a systematic methodology
of design. If we start with a requirements document for the system, we can
design an abstract structure that meets the requirements. We can then decompose
this structure into a collection of components that interact to perform the same function.
Each of these components can in turn be decomposed until we get to a level
where we have some ready-made, primitive components that perform a required
function. The result of this process is a hierarchically composed system, built from
the primitive elements.
The advantage of this methodology is that each subsystem can be designed independently
of others. When we use a subsystem, we can think of it as an abstraction
rather than having to consider its detailed composition. So at any particular stage in
the design process, we only need to pay attention to the small amount of information
relevant to the current focus of design. We are saved from being overwhelmed by
masses of detail.
We use the term model to mean our understanding of a system. The model represents
that information which is relevant and abstracts away from irrelevant detail.
The implication of this is that there may be several models of the same system, since
different information is relevant in different contexts. One kind of model might concentrate
on representing the function of the system, whereas another kind might represent
the way in which the system is composed of subsystems.
There are a number of important motivations for formalizing this idea of a model,
including
• expressing system requirements in a complete and unambiguous way
• documenting the functionality of a system
• testing a design to verify that it performs correctly
4 Fundamental Concepts
• formally verifying properties of a design
• synthesizing an implementation in a target technology (e.g., ASIC or FPGA)
The unifying factor is that we want to achieve maximum reliability in the design
process for minimum cost and design time. We need to ensure that requirements are
clearly specified and understood, that subsystems are used correctly and that designs
meet the requirements. A major contributor to excessive cost is having to revise a
design after manufacture to correct errors. By avoiding errors, and by providing better
tools for the design process, costs and delays can be contained.
2.2 VHDL Modeling Concepts
In this section, we look at the basic VHDL concepts for behavioral and structural modeling.
This will provide a feel for VHDL and a basis from which to work in later chapters.
As an example, we look at ways of describing a four-bit register, shown in
Using VHDL terminology, we call the module reg4 a design entity, and the inputs
and outputs are ports. Figure 2-2 shows a VHDL description of the interface to this
entity. This is an example of an entity declaration. It introduces a name for the entity
and lists the input and output ports, specifying that they carry bit values (‘0’ or ‘1’) into
and out of the entity. From this we see that an entity declaration describes the external
view of the entity.
Elements of Behavior
In VHDL, a description of the internal implementation of an entity is called an architecture
body of the entity. There may be a number of different architecture bodies of
the one interface to an entity, corresponding to alternative implementations that perform
the same function. We can write a behavioral architecture body of an entity,
which describes the function in an abstract way. Such an architecture body includes
only process statements, which are collections of actions to be executed in sequence.
These actions are called sequential statements and are much like the kinds of statements
we see in a conventional programming language. The types of actions that can
be performed include evaluating expressions, assigning values to variables, conditional
execution, repeated execution and subprogram calls. In addition, there is a sequential
statement that is unique to hardware modeling languages, the signal assignment
statement. This is similar to variable assignment, except that it causes the value on a
signal to be updated at some future time.