03-07-2012, 03:48 PM
System-on-Chip Environment
A System-on-Chip.pdf (Size: 5.35 MB / Downloads: 33)
Introduction
The basic purpose of this tutorial is to guide a user through our System-on-Chip design
environment (SCE). SCE helps designers to take an abstract functional description of
the design and produce an implementation. We begin with a brief overview of our SoC
methodology by describing the design flow and various abstraction levels. The overview
also covers the user interfaces and the tools that support the design flow.
We then describe the example that we use throughout this tutorial.We selected the GSM
Vocoder as an example for a variety of reasons. For one, the Vocoder is a fairly large
design and is an apt representative of a typical component of a System-on-Chip design.
Moreover, the functional specification of the Vocoder is well defined and publicly available
from the European Telecommunication Standards Institute (ETSI).
Motivation
System-on-Chip capability introduces new challenges in the design process. For one,
co-design becomes a crucial issue. Software and Hardware must be developed together.
However, both Software and Hardware designers have different views of the system and
they use different design and modeling techniques.
Secondly, the process of system design from specification to mask is long and elaborate.
The process must therefore be split into several steps. At each design step, models must
be written and relevant properties must be verified.
SCE Goals
SCE represents a new technology that allows designers to capture system specification
as a composition of C-functions. These are automatically refined into different models
required at each step of the design process. Therefore designers can devote more effort
to the creative part of designing and the tools can create models for validation and synthesis.
The end result is that the designers do not need to learn new system level design
languages (SystemC, SpecC, Superlog, etc.) or even the existing Hardware Description
Languages (Verilog, VHDL)
System-on-Chip Environment
The SCE provides an environment for modeling, synthesis and validation. It includes a
graphical user interface (GUI) and a set of tools to facilitate the design flow and perform
the aforementioned refinement steps. The two major components of the GUI are the
Refinement User Interface (RUI) on the left and the Validation User Interface (VUI) on
the right as shown in figure 1-1. The RUI allows designers to make and input design
decisions, such as component allocation, specification mapping. With design decisions
made, refinement tools can be invoked inside RUI to refine models. The VUI allows the
simulation of all models to validate the design at each stage of the design flow.
Each of the boxes corresponds to a tool which performs a specific task automatically.
A profiling tool is used to obtain the characteristics of the initial specification, which
serves as the basis for architecture exploration. The refinement tool set automatically
transforms models based on relevant design decisions. The estimation tool set produces
quality metrics for each intermediate models, which can be evaluated by designers.
Specification Capture
The system design process starts with the specification model written by the user to
specify the desired system functionality. It forms the input to the series of exploration
and refinement steps in the SoC design methodology. Moreover, the specification model
defines the granularity for exploration through the size of the leaf behaviors. It exposes
all available parallelism and uses hierarchy to group related functionality and manage
complexity.
In this section, we go through the steps of creating a project in SCE and initiating the
system design process. The various aspects of the specification are observed through
simulation and profiling. Also, the model is graphically viewed with the help of SCE
tools.