17-05-2012, 12:56 PM
POWER OPTIMIZATION OF LINEAR FEEDBACK shift REGISTER(LFSR)FOR LOW POWER
POWER OPTIMIZATION OF LINEAR FEEDBACK shift REGISTER(LFSR)FOR LOW POWER.ppt (Size: 1.11 MB / Downloads: 94)
ABSTRACT
This project proposes a low power LFSR for TPG technique with reducing power dissipation during testing .
The correlations between the consecutive patterns are higher during normal mode than during testing
The proposed approach uses the concept of reduce the transitions in the test pattern generated by conventional LFSR. The transition is reduced by increasing the Correlation between the successive bits.
The main challenging areas in VLSI are
Performance
Cost
Testing
Area
Reliability and Power
SOURCES OF POWER DISSIPATION
STATIC POWER DISSIPATION
DYNAMIC POWER DISSIPATION
REASONS FOR THE POWER INCREASE IN TEST MODE.
Parallel testing.
Delay.
Switching activity.
The effects of large power dissipation
cost
Reliability
Performance verification
Change in logic state
SOME KEY POINTS:-
TESTING
DFT(Design For Testability)
BIST(Built in Self Test)
LFSR(Linear Feedback Shift Register)
MBIST(Memory Built in Self Test)
DESIGN FOR TESTABILITY:
For complex circuits, hierarchical approach is used. The advantage of hierarchical approach is that every block is tested separately. Test input is given to each block and output is observed and verified.
DFT (design for testability) is the action of placing features in a chip design process to enhance the ability to generate vectors, achieve a measured quality level or reduce cost of testing. The conventional DFT approaches use scan and BIST.
In this paper a modified low power LFSR are used in which the number of transitions of test pattern are reduced testing.
BUILT IN SELF TEST:
BIST is the design technique in which parts of a circuits are used to test the circuit itself.
BIST is a Design-for-Testability (DFT) technique, because it makes the electrical testing of a chip easier, faster, more efficient, and less costly.
The concept of BIST is applicable to just about any kind of circuit, so its implementation can vary widely as the product diversity that it caters to.
Advantages of BIST
lower cost of test, since the need for external electrical testing using an ATE will be reduced, if not eliminated.
better fault coverage, since special test structures can be incorporated onto the chips.
shorter test times if the BIST can be designed to test more structures in parallel.
easier customer support.
capability to perform tests outside the production electrical testing environment.
FUTURE WORK
Top module for BISTcontroller
The low power LFSR is coded in verilog hardware description language.
The CUT used is c432,a bench mark circuit of ISCAS-85 is used,the generated code is synthesized in xilinx 9.1
Xpower is used to compare the power reports.
CONCLUSION
After incorporating the so designed algorithm in the LFSR of BIST, it will be verified that the power of the LFSR is reduced.
By using low power LFSR technique, we can observe that the power in BIST implementation can be further decreased.