28-05-2012, 11:18 AM
Reconfigurable Computing Using FPGA: State of the Art and Potential
for Systolic Array Applications
Reconfigurable Computing Using FPGA.pdf (Size: 27.02 KB / Downloads: 42)
Introduction
Our research group is investigating the use of
systolic array processors based on multi FPGA
(field-programmable gate array) technology to
accelerate computational tasks in computation
intensive algorithms. In this paper, we investigate
first the state-of-the-art reconfigurable computing.
We first define the implementation spectrum,
classify and characterize the different level of
abstraction (logic, functional and system). Then,
we review in detail the basic building blocks of
reconfigurable devices, essentially, the fieldprogrammable
gate arrays (FPGAs). As a final
step, we look for potential multi-FPGA systems
and their interconnections in systolic array
applications.
2. Content
Fig. 1 shows the implementation spectrum in
reconfigurable computing [1]. The spectrum is
bounded by three axes symbolising the
performance, flexibility and cost. The figure clearly
shows that ASIC gives high performance at the cost
of inflexibility, processor is very flexible but not
tuned to the application and that RC hardware is a
nice compromise.
Conclusion
Our study shows inter-chip connectivity as an issue
in using gigabit transceivers for High speed FPGAFPGA
connections to make multiple FPGAs more
like one big FPGA and the suitability for spatially
parallel applications using systolic arrays.