17-03-2014, 11:23 AM
3D IC technology
3D IC technology11.ppt (Size: 537 KB / Downloads: 13)
Motivation
Interconnect structures increasingly consume more of the power and delay budgets in modern design
Plausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC design
Smaller wire cross-sections, smaller wire pitch and longer lines to traverse larger chips increase RC delay.
RC delay is increasingly becoming the dominant factor
At 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay.
130 nm technology node, substantial interconnect delays will result.
Performance Characteristics
Timing
Energy
With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced
Design tools for 3D-IC design
Demand for EDA tools
As the technology matures, designers will want to exploit this design area
Current tool-chains
Mostly academic
We will discuss a tool from MIT
Extending to 3D
Routing in 3D consists of routing a set of aligned congruent routing regions on adjacent wafers.
Wires can enter from any of the sides of the routing region in addition to its top and bottom
3D router must consider routing on each of the layers in addition to the placement of the inter-waver vias
Basis idea is: You connect a inter-waver via to the port you are trying to connect to, and route the wire to that via on the 2D plane.
All we need now is enough area in the 2D routing space to route to the appropriate via
Reliability Issues?
Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance
Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.
Conclusion
3D IC design is a relief to interconnect driven IC design.
Still many manufacturing and technological difficulties
Needs strong EDA applications for automated design
3D IC technology11.ppt (Size: 537 KB / Downloads: 13)
Motivation
Interconnect structures increasingly consume more of the power and delay budgets in modern design
Plausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC design
Smaller wire cross-sections, smaller wire pitch and longer lines to traverse larger chips increase RC delay.
RC delay is increasingly becoming the dominant factor
At 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay.
130 nm technology node, substantial interconnect delays will result.
Performance Characteristics
Timing
Energy
With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced
Design tools for 3D-IC design
Demand for EDA tools
As the technology matures, designers will want to exploit this design area
Current tool-chains
Mostly academic
We will discuss a tool from MIT
Extending to 3D
Routing in 3D consists of routing a set of aligned congruent routing regions on adjacent wafers.
Wires can enter from any of the sides of the routing region in addition to its top and bottom
3D router must consider routing on each of the layers in addition to the placement of the inter-waver vias
Basis idea is: You connect a inter-waver via to the port you are trying to connect to, and route the wire to that via on the 2D plane.
All we need now is enough area in the 2D routing space to route to the appropriate via
Reliability Issues?
Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance
Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.
Conclusion
3D IC design is a relief to interconnect driven IC design.
Still many manufacturing and technological difficulties
Needs strong EDA applications for automated design