29-08-2017, 12:28 PM
In this modern era, elevators have become an integral part of any commercial or public complex. It facilitates faster movement of people and luggage between floors. The elevator control system is one of the most important aspects in the electronics control module that are used in the automotive application. Usually elevators are designed for a specific building taking into account the main factors like the height of the building, the number of people traveling to each floor and the expected periods of high usage. The elevator system is designed with different control strategies. This implementation is based on FPGA, which can be used for a building with any number of floors, with the inputs and outputs specified. This controller can be implemented for an elevator with the required number of floors simply by changing a control variable in the HDL code. This approach is based on an algorithm that reduces the amount of computation required, focusing only on the relevant rules that improve the performance of the elevator system group. The elevator controller was developed using Verilog HDL and was successfully implemented in a Xilinx Artix7 FPGA.
An elevator is the vertical transport equipment used to carry luggage or passengers between the floors of a building. Elevators plays a vital role in both commercial and residential areas. Traditional elevator control systems rely mainly on relay logic, PLC and microcontroller, but the main disadvantage of these systems is that they have a reduced number of inputs and outputs. An elevator can be considered as a complex reactive system that requires parallel event processing with a number of inputs and outputs. Therefore, FPGAs make a better solution for implementing an elevator controller with additional reconfigurability advantages, lower power consumption, lower response times and flexibility in design expansion. The elevator control system is basically a finite state machine (FSM).
FPGA or Field Programmable Gate Array consists of the following components:
(I) Programmable Logic Blocks
(Ii) Interconnection Resources
(Iii) The FPGA input output blocks are composed of programmable logic components called "logic blocks" and a hierarchy of reconfigurable interconnects that interconnects the logic blocks.
Logical blocks can be configured to perform simple logic gates such as AND and XOR or even complex combinational functions. In most FPGAs, logic blocks also include memory elements, which can be single flip-flops or complete blocks of memory. Contemporary FPGAs have a large number of logic gates and RAM blocks to implement complex digital functions. It becomes a challenge to verify the correct synchronization of valid data within configuration time and timeout as FPGA designs employ very fast I / O and bidirectional data buses. Plant planning allows the allocation of resources within FPGA to meet these time constraints. FPGAs can be used to implement logical functions that an ASIC could perform. The advantages of FPGA over ASIC include the ability to update its functionality after shipment, partial reconfiguration of a part of the design and low non-recurring engineering costs . Some FPGAs have analog functions in addition to digital features. The most common analog feature is the programmable transmission force and rotation speed at each of the output pins, allowing slow speeds to be set on slightly charged pins that would otherwise unacceptably touch or engage to establish stronger and faster speeds on pins loaded into high-speed channels that would otherwise run too slowly. Another common analog feature is differential comparators. FPGAs can be reprogrammed for the desired functionality requirements after manufacture. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are specifically designed for specific design tasks
An elevator is the vertical transport equipment used to carry luggage or passengers between the floors of a building. Elevators plays a vital role in both commercial and residential areas. Traditional elevator control systems rely mainly on relay logic, PLC and microcontroller, but the main disadvantage of these systems is that they have a reduced number of inputs and outputs. An elevator can be considered as a complex reactive system that requires parallel event processing with a number of inputs and outputs. Therefore, FPGAs make a better solution for implementing an elevator controller with additional reconfigurability advantages, lower power consumption, lower response times and flexibility in design expansion. The elevator control system is basically a finite state machine (FSM).
FPGA or Field Programmable Gate Array consists of the following components:
(I) Programmable Logic Blocks
(Ii) Interconnection Resources
(Iii) The FPGA input output blocks are composed of programmable logic components called "logic blocks" and a hierarchy of reconfigurable interconnects that interconnects the logic blocks.
Logical blocks can be configured to perform simple logic gates such as AND and XOR or even complex combinational functions. In most FPGAs, logic blocks also include memory elements, which can be single flip-flops or complete blocks of memory. Contemporary FPGAs have a large number of logic gates and RAM blocks to implement complex digital functions. It becomes a challenge to verify the correct synchronization of valid data within configuration time and timeout as FPGA designs employ very fast I / O and bidirectional data buses. Plant planning allows the allocation of resources within FPGA to meet these time constraints. FPGAs can be used to implement logical functions that an ASIC could perform. The advantages of FPGA over ASIC include the ability to update its functionality after shipment, partial reconfiguration of a part of the design and low non-recurring engineering costs . Some FPGAs have analog functions in addition to digital features. The most common analog feature is the programmable transmission force and rotation speed at each of the output pins, allowing slow speeds to be set on slightly charged pins that would otherwise unacceptably touch or engage to establish stronger and faster speeds on pins loaded into high-speed channels that would otherwise run too slowly. Another common analog feature is differential comparators. FPGAs can be reprogrammed for the desired functionality requirements after manufacture. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are specifically designed for specific design tasks