12-09-2017, 11:40 AM
In this ADPLL the phase detection system is performed by generating an analytical signal using a compact implementation of the Hilbert transform and simply calculating the instantaneous phase using the algorithm CORDIC in vector mode of operation. A 16-bit CORDIC algorithm is used to obtain the phase information of the signal. All components used in this phase detection system are made as discrete-time digital components. This design does not involve any kind of multipliers, thus reducing the complexity of the design. The ADPLL loop filter has been designed using a PI controller that has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to calculate sinusoidal values for the DDS.
As components for digital signal processing are constantly improving, more and more applications of processing signals in the radio frequency (RF) range are moving from the analog to the digital domain. The advantages of multiple as high accuracy, perfect predictability and the possibility of using more complexity while no calibration is necessary are obvious. The motivation of this work arose from the need for a local offset oscillator (LO offset) in a fast phase detection system for closed loop RF controls in the SIS18 heavy ion particle accelerator in GSI . Since the signal frequencies of that application are in the tens of MHz range, the processing power of a microcontroller with integrated ADC and DAC is insufficient while designing a custom ASIC for quantities of a few hundred is too expensive. This scope of application is covered by FPGAs, which play an important role in high energy physics experiments , as they offer the speed, density and computing power that otherwise are only achievable with ASICS and are flexible as the microcontrollers (in terms or configurability). Therefore, an FPGA with fast ADC and DAC converters was chosen as the platform for the LO offset based on a discrete all-digital PLL (ADPLL).
As components for digital signal processing are constantly improving, more and more applications of processing signals in the radio frequency (RF) range are moving from the analog to the digital domain. The advantages of multiple as high accuracy, perfect predictability and the possibility of using more complexity while no calibration is necessary are obvious. The motivation of this work arose from the need for a local offset oscillator (LO offset) in a fast phase detection system for closed loop RF controls in the SIS18 heavy ion particle accelerator in GSI . Since the signal frequencies of that application are in the tens of MHz range, the processing power of a microcontroller with integrated ADC and DAC is insufficient while designing a custom ASIC for quantities of a few hundred is too expensive. This scope of application is covered by FPGAs, which play an important role in high energy physics experiments , as they offer the speed, density and computing power that otherwise are only achievable with ASICS and are flexible as the microcontrollers (in terms or configurability). Therefore, an FPGA with fast ADC and DAC converters was chosen as the platform for the LO offset based on a discrete all-digital PLL (ADPLL).