18-10-2010, 04:59 PM
3D.ppt (Size: 626.5 KB / Downloads: 396)
This article is presented by:Pouya Dormiani
Christopher Lucas
3D IC technology
Motivation
Interconnect structures increasingly consume more of the power and delay budgets in modern design
Plausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC design
Smaller wire cross-sections, smaller wire pitch and longer lines to traverse larger chips increase RC delay.
RC delay is increasingly becoming the dominant factor
At 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay.
130 nm technology node, substantial interconnect delays will result.
3D Fabrication Technologies
Many options available for realization of 3D circuits
Choice of Fabrication depends on requirements of Circuit System
Performance Characteristics
Timing
Energy
With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced
Timing
In current technologies, timing is interconnect driven.
Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance
The graph below shows the results of a reduction in wire length due to 3D routing
Discussed more in detail later in the slides