12-04-2011, 04:52 PM
PRESENTED BY:
ARUN KUMAR PANDEY
PREETAM KUMAR
Silicon On Insulator.pptx (Size: 5.58 MB / Downloads: 130)
S.O.I.(SILICON ON INSULATOR)
INTRODUCTION:
Latest fabrication technology.
Chip in a Blanket.
Silicon-on-Silicon.
Increasing demand for high performance, low power & low area among micro-electronic device led to its invention.
INVENTION:
SOI (silicon-on-insulator) has been known for ~ 20 years.
In 1993 Honeywell started product development of SOI to support commercial aircraft electronic engine controls.
First it was used for military purposes in U.S.A.
What is soi ?
It is the latest fabrication technique.
It is easier & cheaper.
Transistors are build on a silicon layer resting on insulating layer of silicon-di-oxide known as BOX (burried oxide).
Only a thin layer from a face of the wafer used for making electronic components, the rest essentially serves as mechanical support.
To enhance the performance
Higher speed.
Less power consumption.
Easier fabrication.
Cheaper etching process.
More electronic devices can be fabricated on same chip (30% more than bulk).
It reduces parasitic capacitance when compared to bulk or epi-wafers.
ARUN KUMAR PANDEY
PREETAM KUMAR
Silicon On Insulator.pptx (Size: 5.58 MB / Downloads: 130)
S.O.I.(SILICON ON INSULATOR)
INTRODUCTION:
Latest fabrication technology.
Chip in a Blanket.
Silicon-on-Silicon.
Increasing demand for high performance, low power & low area among micro-electronic device led to its invention.
INVENTION:
SOI (silicon-on-insulator) has been known for ~ 20 years.
In 1993 Honeywell started product development of SOI to support commercial aircraft electronic engine controls.
First it was used for military purposes in U.S.A.
What is soi ?
It is the latest fabrication technique.
It is easier & cheaper.
Transistors are build on a silicon layer resting on insulating layer of silicon-di-oxide known as BOX (burried oxide).
Only a thin layer from a face of the wafer used for making electronic components, the rest essentially serves as mechanical support.
To enhance the performance
Higher speed.
Less power consumption.
Easier fabrication.
Cheaper etching process.
More electronic devices can be fabricated on same chip (30% more than bulk).
It reduces parasitic capacitance when compared to bulk or epi-wafers.