31-05-2012, 03:19 PM
DSP Processor
DSP Processor.ppt (Size: 287.5 KB / Downloads: 92)
High speed DSP computations
Specialized instruction set
High performance repetitive numeric calculations
Fast & efficient memory accesses
Special mechanism for real-time I/O
Low power consumption
Low cost in comparison with GPPs
DSPs μPs Applications
Speech and audio compression
Filtering
Modulation and demodulation
Error correction coding and decoding
Audio processing (e.g., surround sound, noise reduction, equalization, sample rate conversion, echo cancellation)
Signaling (e.g., DTMF detection)
Speech recognition
Signal synthesis (e.g., music, speech synthesis).
DSPs Characteristics
Data path & internal ALU architecture
Specialized instruction set
External memory architecture
Specialized addressing modes
Specialized execution control
Specialized peripherals for DSP
VLIW
Very long instruction word (VLIW) architectures are garnering increased attention for DSP applications.
Major features:
Multiple independent operations per cycle
Packed into a single large “instruction” or “packet”
More regular, orthogonal, RISC-like operations Large, uniform register sets
DSP Processor.ppt (Size: 287.5 KB / Downloads: 92)
High speed DSP computations
Specialized instruction set
High performance repetitive numeric calculations
Fast & efficient memory accesses
Special mechanism for real-time I/O
Low power consumption
Low cost in comparison with GPPs
DSPs μPs Applications
Speech and audio compression
Filtering
Modulation and demodulation
Error correction coding and decoding
Audio processing (e.g., surround sound, noise reduction, equalization, sample rate conversion, echo cancellation)
Signaling (e.g., DTMF detection)
Speech recognition
Signal synthesis (e.g., music, speech synthesis).
DSPs Characteristics
Data path & internal ALU architecture
Specialized instruction set
External memory architecture
Specialized addressing modes
Specialized execution control
Specialized peripherals for DSP
VLIW
Very long instruction word (VLIW) architectures are garnering increased attention for DSP applications.
Major features:
Multiple independent operations per cycle
Packed into a single large “instruction” or “packet”
More regular, orthogonal, RISC-like operations Large, uniform register sets