02-09-2017, 12:17 PM
With the proliferation of portable electronic devices, energy-efficient data transmission has become increasingly important. For serial data transfer, Universal Asynchronous Receiver / Transmitter (UART) circuits are often implemented because of their simplicity of inherent design and application-specific versatility.
Components such as laptop keyboards, palm pilot organizers and modems are few examples of devices employing UART circuits. In this work, the design and analysis of a robust UART architecture has been carried out to minimize energy consumption during both standby and continuous modes of operation.
A UART (universal asynchronous receiver / transmitter) is responsible for performing the primary task in serial communications with computers. The device switches the incoming parallel information to serial data that can be sent on a communication line. A second UART can be used to receive the information. The UART performs all tasks, time, parity control, etc. necessary for communication. The only additional devices connected are line controller chips capable of transforming TTL level signals into line voltages and vice versa.
To use the device in different environments, the logs are accessible to establish or review the communication parameters. The adjustable parameters are, for example, the communication speed, the type of parity check and the way the incoming information is indicated to the running software.
Serial communication on compatible PCs started with the 8250 UART on the XT. In the years after, new family members such as revisions 8250A and 8250B and 16450 were introduced.
The latter was implemented for the first time in the TA. The highest bus speed in this equipment could not be reached by the 8250 series. The differences between these first series of UART were quite minor. The most important property changed with each new version was the maximum speed allowed on the side of the processor bus.
The 16450 was able to handle a communication speed of 38.4 kbs without problems. The demand for higher speeds led to the development of new series that could free the main processor from some of its tasks. The main problem with the original series was the need to perform a software action for each single byte to transmit or receive. To overcome this problem, the 16550 was released which contained two on-board FIFO buffers, each capable of storing 16 bytes. A buffer for input and a buffer for outgoing bytes.
Components such as laptop keyboards, palm pilot organizers and modems are few examples of devices employing UART circuits. In this work, the design and analysis of a robust UART architecture has been carried out to minimize energy consumption during both standby and continuous modes of operation.
A UART (universal asynchronous receiver / transmitter) is responsible for performing the primary task in serial communications with computers. The device switches the incoming parallel information to serial data that can be sent on a communication line. A second UART can be used to receive the information. The UART performs all tasks, time, parity control, etc. necessary for communication. The only additional devices connected are line controller chips capable of transforming TTL level signals into line voltages and vice versa.
To use the device in different environments, the logs are accessible to establish or review the communication parameters. The adjustable parameters are, for example, the communication speed, the type of parity check and the way the incoming information is indicated to the running software.
Serial communication on compatible PCs started with the 8250 UART on the XT. In the years after, new family members such as revisions 8250A and 8250B and 16450 were introduced.
The latter was implemented for the first time in the TA. The highest bus speed in this equipment could not be reached by the 8250 series. The differences between these first series of UART were quite minor. The most important property changed with each new version was the maximum speed allowed on the side of the processor bus.
The 16450 was able to handle a communication speed of 38.4 kbs without problems. The demand for higher speeds led to the development of new series that could free the main processor from some of its tasks. The main problem with the original series was the need to perform a software action for each single byte to transmit or receive. To overcome this problem, the 16550 was released which contained two on-board FIFO buffers, each capable of storing 16 bytes. A buffer for input and a buffer for outgoing bytes.