27-04-2011, 11:17 AM
PRESENTED BY:
Roy Vincent
3D IC Seminar Presentation.pptx (Size: 4.38 MB / Downloads: 41)
Three Dimensional Integrated Circuits
No Trend Remains Constant Forever
Unfortunately the case with Moore’s law is the same
CURRENT SCENARIO
Is There Any Other Solution?
DEFINITION
3D IC Is NOT 3D Packing
The Making Of A Three Dimensional Integrated Circuit
PROCESS FACTORS
PROCESS FACTORS
STRATA ORIENTATION
BONDING INTERFACE DESIGN
BONDING INTERFACE DESIGN
BONDING INTERFACE DESIGN
THROUGH SILICON VIA
THERMAL AND POWER DELIVERY CHALLENGES
Circuit is much denser than 2D technology
For the same footprint, and similar packing technology, a k- tier 3D chip could use k times as much current as a single 2D chip
So if thermal consideration is not taken, 3D chip will be k times hotter than a 2D chip
Supplying power to all layers is a very difficult task
TACKLING THERMAL PROBLEMS
Low-power design
Rearranging the heat sources
Improving thermal conduits
Improving the heat sink
POWER SUPPLY ISSUES
Supplying power to all layers is a very difficult task
On-chip power supply noise has worsened due to scaling of the power supply network (PSN)
The increased IR and Ldi/dt supply noise in 3D chips may cause a larger variation in operating speed leading to more timing violations
Overshoot due to inductive parasitic may cause reliability issues like oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI)
TACKLING POWER DISTRIBUTION PROBLEM
ON-CHIP VOLTAGE REGULATION
DC–DC converter module closer to the processor
Boosting the external voltage and locally down converting
Size of inductors are a problem
Though costly, thin film inductors give excellent result
Heterogeneous technologies must be used, which is easy in 3D IC
Z-AXIS POWER DELIVERY
MULTISTORY POWER DELIVERY (MSPD)
FLOORPLAN
THERMAL-AWARE 3D FLOORPLAN
FLOORPLANNING APPROACH IN 3D IC
Three-Dimensional Microprocessor Design
STACKING COMPLETE MODULES
STACKING COMPLETE MODULES
STACKING FUNCTIONAL UNIT BLOCKS
SPLITTING FUNCTIONAL UNIT BLOCKS
Pros And Cons Of 3D Stacking At Different Granularities
CONCLUSION
Roy Vincent
3D IC Seminar Presentation.pptx (Size: 4.38 MB / Downloads: 41)
Three Dimensional Integrated Circuits
No Trend Remains Constant Forever
Unfortunately the case with Moore’s law is the same
CURRENT SCENARIO
Is There Any Other Solution?
DEFINITION
3D IC Is NOT 3D Packing
The Making Of A Three Dimensional Integrated Circuit
PROCESS FACTORS
PROCESS FACTORS
STRATA ORIENTATION
BONDING INTERFACE DESIGN
BONDING INTERFACE DESIGN
BONDING INTERFACE DESIGN
THROUGH SILICON VIA
THERMAL AND POWER DELIVERY CHALLENGES
Circuit is much denser than 2D technology
For the same footprint, and similar packing technology, a k- tier 3D chip could use k times as much current as a single 2D chip
So if thermal consideration is not taken, 3D chip will be k times hotter than a 2D chip
Supplying power to all layers is a very difficult task
TACKLING THERMAL PROBLEMS
Low-power design
Rearranging the heat sources
Improving thermal conduits
Improving the heat sink
POWER SUPPLY ISSUES
Supplying power to all layers is a very difficult task
On-chip power supply noise has worsened due to scaling of the power supply network (PSN)
The increased IR and Ldi/dt supply noise in 3D chips may cause a larger variation in operating speed leading to more timing violations
Overshoot due to inductive parasitic may cause reliability issues like oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI)
TACKLING POWER DISTRIBUTION PROBLEM
ON-CHIP VOLTAGE REGULATION
DC–DC converter module closer to the processor
Boosting the external voltage and locally down converting
Size of inductors are a problem
Though costly, thin film inductors give excellent result
Heterogeneous technologies must be used, which is easy in 3D IC
Z-AXIS POWER DELIVERY
MULTISTORY POWER DELIVERY (MSPD)
FLOORPLAN
THERMAL-AWARE 3D FLOORPLAN
FLOORPLANNING APPROACH IN 3D IC
Three-Dimensional Microprocessor Design
STACKING COMPLETE MODULES
STACKING COMPLETE MODULES
STACKING FUNCTIONAL UNIT BLOCKS
SPLITTING FUNCTIONAL UNIT BLOCKS
Pros And Cons Of 3D Stacking At Different Granularities
CONCLUSION